參數(shù)資料
型號(hào)： ADV7341
廠商： Analog Devices, Inc.
英文描述： Multiformat Video Encoder, Six 12-Bit Noise Shaped Video㈢ DACS
中文描述： 多格式視頻編碼器，6個(gè)12位噪聲整形視頻㈢交叉連接系統(tǒng)
文件頁(yè)數(shù)： 29/88頁(yè)
文件大?。?/td> 1066K
代理商： ADV7341
ADV7340/ADV7341
Rev. 0 | Page 29 of 88
Table 15. Register 0x01 to Register 0x09
SR7 to
SR0
Register
0x01
Mode Select
Register
Bit Description
Reserved.
DDR Clock Edge Alignment.
Note: Only used for ED
1
and
HD DDR modes.
Bit Number
5
4
Register Setting
Chroma clocked in on rising clock edge;
luma clocked in on falling clock edge.
Reserved.
Reserved.
Luma clocked in on rising clock edge;
chroma clocked in on falling clock edge.
SD input only.
ED/HD-SDR input only.
ED/HD-DDR input only.
SD and ED/HD-SDR.
SD and ED/HD-DDR.
Reserved.
Reserved.
ED only (at 54 MHz).
Allows data to be applied to data ports in
various configurations (SD feature only).
Reset
Value
0x00
7
6
3
2
0
1
0
0
0
0
1
1
1
0
1
Reserved.
Input Mode.
Note: See Reg. 0x30, Bits[7:3]
for ED/HD format selection.
0
1
0
0
0
0
1
1
1
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
0
Y/C/S Bus Swap.
Reserved.
Test Pattern Black Bar.
2
0 must be written to these bits.
Disabled.
Enabled.
Disable manual CSC matrix adjust.
Enable manual CSC matrix adjust.
No sync.
Sync on all RGB outputs.
RGB component outputs.
YPrPb component outputs.
No sync output.
Output SD syncs on S_HSYNC and
S_VSYNC pins.
No sync output.
Output ED/HD syncs on S_HSYNC and
S_VSYNC pins.
LSBs for GY.
0x20
Manual CSC Matrix Adjust.
Sync on RGB.
RGB/YPrPb Output Select.
SD Sync Output Enable.
0
1
0x02
Mode
Register 0
ED/HD Sync Output Enable.
0x03
ED/HD CSC
Matrix 0
ED/HD CSC
Matrix 1
x
x
0x03
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
LSBs for RV.
LSBs for BU.
LSBs for GV.
LSBs for GU.
Bits[9:2 ] for GY.
0xF0
0x04
0x05
ED/HD CSC
Matrix 2
ED/HD CSC
Matrix 3
ED/HD CSC
Matrix 4
ED/HD CSC
Matrix 5
ED/HD CSC
Matrix 6
0x4E
0x06
x
x
x
x
x
x
x
x
Bits[9:2] for GU.
0x0E
0x07
x
x
x
x
x
x
x
x
Bits[9:2] for GV.
0x24
0x08
x
x
x
x
x
x
x
x
Bits[9:2] for BU.
0x92
0x09
x
x
x
x
x
x
x
x
Bits[9:2] for RV.
0x7C
1
ED = enhanced definition = 525p and 625p.
2
Subaddress 0x31, Bit 2 must also be enabled (ED/HD). Subaddress 0x84, Bit 6 must also be enabled (SD).
相關(guān)PDF資料
PDF描述
ADV7341BSTZ Multiformat Video Encoder, Six 12-Bit Noise Shaped Video㈢ DACS
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ADV7343BSTZ Multiformat Video Encoder Six, 11-Bit, 297 MHz DACs
ADV7342 Multiformat Video Encoder Six, 11-Bit, 297 MHz DACs
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參數(shù)描述
ADV7341BSTZ 制造商:Analog Devices 功能描述:Video Encoder 6DAC 12-Bit 64-Pin LQFP Tray 制造商:Analog Devices 功能描述:MULTI-FORMAT VIDEO ENCODER SIX 12-BIT NOISE SHAPED VIDEO DAC - Bulk
ADV7341EBZ 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Video Encoder, Six 12-Bit Noise Shaped Video㈢ DACS
ADV7342 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Video Encoder Six, 11-Bit, 297 MHz DACs
ADV7342BSTZ 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Video Encoder Six, 11-Bit, 297 MHz DACs
ADV7343 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Video Encoder Six, 11-Bit, 297 MHz DACs
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