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ADV7320/ADV7321
Adaptive Filter Control Application
Figure 75 and Figure 76 show typical signals to be processed by
the adaptive filter control block.
Rev. 0 | Page 57 of 88
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Figure 75. Input Signal to Adaptive Filter Control
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Figure 76. Output Signal after Adaptive Filter Control
The register settings in Table 35 were used to obtain the results
shown in Figure 76, i.e., to remove the ringing on the Y signal.
Input data was generated by an external signal source.
Table 35. Register Settings for Figure 76
Address
Register Setting
0x00
0xFC
0x01
0x38
0x02
0x20
0x10
0x00
0x11
0x81
0x15
0x80
0x20
0x00
0x38
0xAC
0x39
0x9A
0x3A
0x88
0x3B
0x28
0x3C
0x3F
0x3D
0x64
When changing the adaptive filter mode to Mode B
[Address 0x15, Bit 6], the output shown in Figure 77 can be
obtained.
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Figure 77. Output Signal from Adaptive Filter Control
SD DIGITAL NOISE REDUCTION
[Subaddresses 0x63, 0x64, 0x65]
DNR is applied to the Y data only. A filter block selects the high
frequency, low amplitude components of the incoming signal
(DNR input select). The absolute value of the filter output is
compared to a programmable threshold value (DNR threshold
control). There are two DNR modes available: DNR mode and
DNR sharpness mode.
In DNR mode, if the absolute value of the filter output is
smaller than the threshold, it is assumed to be noise. A
programmable amount (coring gain border, coring gain data) of
this noise signal will be subtracted from the original signal. In
DNR sharpness mode, if the absolute value of the filter output is
less than the programmed threshold, it is assumed to be noise,
as before. Otherwise, if the level exceeds the threshold, now
being identified as a valid signal, a fraction of the signal (coring
gain border, coring gain data) will be added to the original
signal to boost high frequency components and sharpen the
video image.
In MPEG systems, it is common to process the video
information in blocks of 8 pixels × 8 pixels for MPEG2 systems,
or 16 pixels × 16 pixels for MPEG1 systems (block size control).
DNR can be applied to the resulting block transition areas that
are known to contain noise. Generally, the block transition area
contains two pixels. It is possible to define this area to contain
four pixels (border area).
It is also possible to compensate for variable block positioning
or differences in YCrCb pixel timing with the use of the DNR
block offset.
The digital noise reduction registers are three 8-bit registers.
They are used to control the DNR processing.