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| 型號： | ADV7321KSTZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP64 |
| 封裝： | LEAD FREE, PLASTIC, MS-026BCD, LQFP-64 |
| 文件頁數(shù)： | 28/88頁 |
| 文件大?。?/td> | 1002K |
| 代理商： | ADV7321KSTZ |
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ADV7320/ADV7321
Table 10. Register 0x12
SR7–
SR0
Register
0x12
HD Mode
Register 3
Rev. 0 | Page 28 of 88
Bit Description
HD Y Delay with Respect
to Falling Edge of HSYNC
Bit 7
0
1
Bit 6
0
1
Bit 5
0
0
0
0
1
Bit 4
0
0
1
1
0
Bit 3
0
1
0
1
0
Bit 2
0
0
0
0
1
Bit 1
0
0
1
1
0
Bit 0
0
1
0
1
0
Register Setting
0 clk cycles
1 clk cycles
2 clk cycles
3 clk cycles
4 clk cycles
0 clk cycles
1 clk cycle
2 clk cycles
3 clk cycles
4 clk cycles
Disabled
Enabled
Disabled
Enabled
Reset
Values
0x00
HD Color Delay with
Respect to Falling Edge of
HSYNC
HD CGMS
HD CGMS CRC
Table 11. Registers 0x13 to 0x14
SR7–
SR0
Register
0x13
HD Mode
Register 4
Bit Description
HD Cr/Cb Sequence
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Register Setting
Cb after falling edge of HSYNC.
Cr after falling edge of HSYNC.
0 must be written to this bit.
8-bit input.
10-bit input.
Disabled.
Enabled.
0 must be written to this bit.
Disabled.
Enabled.
4:4:4
4:2:2
Disabled.
Enabled.
A low-high-low transition
resets the internal HD timing
counters.
Reset
Values
0x4C
1
Reserved
HD Input Format
0
1
0
1
0
1
0
0
1
0
1
0
x
Sinc Filter on DAC D, E, F
Reserved
HD Chroma SSAF
HD Chroma Input
HD Double Buffering
HD Timing Reset
0x00
0
0
1
0
1
HD Hsync Generation
1
HD Vsync Generation
1
Refer to the / Output Control
section.
BLANK active high.
BLANK active low.
Macrovision disabled.
Macrovision enabled.
0 must be written to these bits.
HD Blank Polarity
1
0
0
1
HD Macrovision for 525p
and 625p
Reserved
0
1
0 = field input.
1 = VSYNC input.
Update field/line counter.
Field/line counter free running.
HD VSYNC/Field Input
0
1
0x14
HD Mode
Register 5
Horizontal/Vertical
Counters
2
1
Used in conjunction with HD_SYNC in Register 0x02, Bit 7 set to 1.
2
When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the standard selected. When set to 1, the
horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.
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