參數(shù)資料
型號(hào)： ADV7305AKST
廠(chǎng)商： ANALOG DEVICES INC
元件分類(lèi)： 顏色信號(hào)轉(zhuǎn)換
英文描述： Multiformat SD, Progressive Scan/HDTV Video Encoder with Six NSV 14-Bit DACs
中文描述： COLOR SIGNAL ENCODER, PQFP64
封裝： PLASTIC, MS-026BCD, LQFP-64
文件頁(yè)數(shù)： 58/68頁(yè)
文件大?。?/td> 2007K
代理商： ADV7305AKST
REV. A
ADV7304A/ADV7305A
Appendix E
–58–
SD TIMING MODES
[Subaddress 4Ah]
Mode 0 (CCIR-656): Slave Option
(Timing Register 0 TR0 = X X X X X 0 0 0)
The ADV7304A/ADV7305A is controlled by the start active video
(SAV) and end active video (EAV) time codes in the pixel data. All
timing information is transmitted using a 4-byte synchronization
pattern. A synchronization pattern is sent immediately before and
after each line during active picture and retrace.
S_VSYNC
,
S_HSYNC
, and
S_BLANK
(if not used) pins should be tied high
during this mode. Blank output is available.
Y
C
r
Y
F
F
0
0
0
0
X
Y
8
0
1
0
8
0
1
0
F
F
0
0
F
F
A
B
A
B
A
B
8
0
1
0
8
0
1
0
F
F
0
0
0
0
X
Y
C
b
YC
r
C
b
Y
C
b
Y
C
r
EAV CODE
SAV CODE
ANCILLARY DATA
(HANC)
268 CLOCK
4 CLOCK
4 CLOCK
1440 CLOCK
4 CLOCK
4 CLOCK
280 CLOCK
1440 CLOCK
END OF ACTIVE
VIDEO LINE
START OF ACTIVE
VIDEO LINE
ANALOG
VIDEO
INPUT PIXELS
NTSC/PAL M SYSTEM
(525 LINES/60Hz)
PAL SYSTEM
(625 LINES/50Hz)
Y
Figure 94. SD Slave Mode 0
Mode 0 (CCIR-656): Master Option
(Timing Register 0 TR0 = X X X X X 0 0 1)
The ADV7304A/ADV7305A generates H, V, and F signals
required for the SAV and EAV time codes in the CCIR-656
standard. The H Bit is output on the
S_HSYNC
pin, the V Bit
is output on the
S_BLANK
pin, and the F Bit is output on the
S_VSYNC
pin.
522
523
524
525
1
2
3
4
5
6
7
8
9
10
11
20
21
22
DISPLAY
DISPLAY
VERTICAL BLANK
ODD FIELD
EVEN FIELD
H
V
F
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
ODD FIELD
EVEN FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
H
V
F
Figure 95. SD Master Mode 0, NTSC
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