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參數(shù)資料
| 型號(hào)： | ADV7305AKST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號(hào)轉(zhuǎn)換 |
| 英文描述： | Multiformat SD, Progressive Scan/HDTV Video Encoder with Six NSV 14-Bit DACs |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP64 |
| 封裝： | PLASTIC, MS-026BCD, LQFP-64 |
| 文件頁數(shù)： | 25/68頁 |
| 文件大小： | 2007K |
| 代理商： | ADV7305AKST |
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REV. A
ADV7304A/ADV7305A
–25–
Table VIII. SD Registers
Subaddress
Register
Bit Description
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
Reset
4Ah
SD Timing Register 0
SD Slave/Master Mode
0
Slave Mode
1
Master Mode
SD Timing Mode
0
0
Mode 0
0
1
Mode 1
1
0
Mode 2
1
1
Mode 3
SD
BLANK
Input
0
Enabled
1
Disabled
SD Luma Delay
0
0
No Delay
0
1
2 Clock Cycles
1
0
4 Clock Cycles
1
1
6 Clock Cycles
SD Min. Luma Value
0
–40 IRE
1
–7.5 IRE
SD Timing Reset
X
0
0
0
0
0
0
0
A low-high-low
transistion will reset the
internal SD timing
counters.
Ta = 1 Clock Cycle
4Bh
SD Timing Register 1
0
0
0
1
Ta = 4 Clock Cycles
1
0
Ta = 16 Clock Cycles
1
1
Ta = 128 Clock Cycles
0
0
Tb = 0 Clock Cycle
0
1
Tb = 4 Clock Cycles
1
0
Tb = 8 Clock Cycles
1
1
Tb = 18 Clock Cycles
X
0
Tc = Tb
X
1
Tc = Tb + 32 μs
0
0
1 Clock Cycle
0
1
4 Clock Cycles
1
0
16 Clock Cycles
1
1
128 Clock Cycles
0
0
0 Clock Cycle
0
1
1 Clock Cycle
1
0
2 Clock Cycles
1
1
3 Clock Cycles
4Ch
SD F
SC
Register 0
X
X
X
X
X
X
X
X
Subcarrier Frequency
Bits 7–0
Subcarrier Frequency
Bits 15–8
Subcarrier Frequency
Bits 23–16
Subcarrier Frequency
Bits 31–24
Subcarrier Phase Bits
9–2
Extended Data Bits 7–0 00h
16h
4Dh
SD F
SC
Register 1
X
X
X
X
X
X
X
X
7Ch
4Eh
SD F
SC
Register 2
X
X
X
X
X
X
X
X
F0h
4Fh
SD F
SC
Register 3
X
X
X
X
X
X
X
X
21h
50h
SD F
SC
Phase
X
X
X
X
X
X
X
X
00h
51h
SD Closed Captioning Extended Data on Even
Fields
X
X
X
X
X
X
X
X
52h
SD Closed Captioning Extended Data on Even
Fields
Data on Odd Fields
X
X
X
X
X
X
X
X
Extended Data Bits
15–8
Data Bits 7–0
00h
53h
SD Closed Captioning
X
X
X
X
X
X
X
X
00h
54h
SD Closed Captioning
Data on Odd Fields
X
X
X
X
X
X
X
X
Data Bits 15–8
00h
55h
SD Pedestal Register 0 Pedestal on Odd Fields
17
16
15
14
13
12
11
10
00h
56h
SD Pedestal Register 1 Pedestal on Odd Fields
25
24
23
22
21
20
19
18
00h
57h
SD Pedestal Register 2 Pedestal on Even Fields
17
16
15
14
13
12
11
10
00h
58h
SD Pedestal Register 3 Pedestal on Even Fields
25
24
23
22
21
20
19
18
00h
Setting any of these bits
to 1 will disable
pedestal on the line
number indicated by
the bit settings.
08h
00h
SD
HSYNC
to
VSYNC
Delay
HSYNC
to Pixel Data
Adjust
SD
HSYNC
to
VSYNC
Rising Edge Delay (Mode 1
Only); VSYNC Width
(Mode 2 Only)
SD
HSYNC
Width
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