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參數(shù)資料
| 型號： | ADV7304A |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat SD, Progressive Scan/HDTV Video Encoder with Six NSV 14-Bit DACs |
| 中文描述： | 多格式統(tǒng)計(jì)，逐行掃描/ HDTV視頻編碼器與六噪聲整形14位DAC |
| 文件頁數(shù)： | 16/68頁 |
| 文件大?。?/td> | 2007K |
| 代理商： | ADV7304A |
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REV. A
ADV7304A/ADV7305A
–16–
Table I. Power Mode Register
Subaddress
Register
Bit Description
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
Reset
00h
Power Mode Register
Sleep Mode
1
0
Sleep Mode Off
1
Sleep Mode On
PLL and Oversampling
Control
0
PLL On
1
PLL Off
DAC F: Power On/Off
0
DAC F Off
1
DAC F On
DAC E: Power On/Off
0
DAC E Off
1
DAC E On
DAC D: Power On/Off
0
DAC D Off
1
DAC D On
DAC C: Power On/Off
0
DAC C Off
1
DAC C On
DAC B: Power On/Off
0
DAC B Off
1
DAC B On
DAC A: Power On/Off
0
DAC A Off
1
DAC A On
Fch
NOTES
1
When enabled, the current consumption is reduced to
μ
A level. All DACs and the internal PLL circuit are disabled. I
2
C registers can be read from and written to.
2
This control allows the internal PLL circuit to be powered down and the oversampling to be switched off.
Table II. Input Mode Register
Subaddress Register
01h
Bit Description
BTA T-1004 Compatibility
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
Reset
38h
Input Mode Register
0
Disabled
1
Enabled
Reserved
0
Zero must be written
to this bit.
Video input data starts
with a Y0 bit. Only for
PS Interleaved Mode.
Video input data starts
with a Cb0 bit.
0
1
0
1
Must be set if the
phase delay between
the two input clocks is
<9.25 ns or >27.75 ns.
Only if two input
clocks are used.
SD Input Only
0
0
0
0
0
1
PS Input Only
0
1
0
HDTV Input Only
0
1
1
SD and PS (20-Bit)
1
0
0
SD and PS (10-Bit)
1
0
1
SD and HDTV (SD
Oversampled)
SD and HDTV
(HDTV Oversampled)
1
1
0
1
1
1
PS 54 MHz Input
Reserved
0
Zero must be written
to this bit.
Pixel Align
Clock Align
Input Mode
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