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參數(shù)資料
| 型號： | ADV7301A |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat SD, Progressive Scan/HDTV Video Encoder with Six NSV⑩ 12-Bit DACs |
| 中文描述： | 多格式統(tǒng)計，逐行掃描/ HDTV視頻編碼器與六噪聲整形⑩12位DAC |
| 文件頁數(shù)： | 57/68頁 |
| 文件大?。?/td> | 1544K |
| 代理商： | ADV7301A |
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REV. A
ADV7300A/ADV7301A
–57–
Table XXVIII. NTSC CVBS Output on DAC A
Subaddress
Register Setting
00h
11h
40h
42h
44h
4Ah
4Ch
4Dh
4Eh
4Fh
82h
01h
10h
40h
40h
08h
16h
7Ch
F0h
21h
All other registers are set to 00h.
For PAL CVBS output on DAC A, the same settings in
Table XXVIII are used except those listed in Table XXIX.
Table XXIX. PAL CVBS Output on DAC A
Subaddress
Register Setting
40h
4Ch
4Dh
4Eh
4Fh
11h
CBh
8Ah
09h
2Ah
Table XXX. NTSC Black Bar Pattern Output on DAC A
Subaddress
Register Setting
00h
02h
11h
40h
42h
44h
4Ah
4Ch
4Dh
4Eh
4Fh
82h
04h
01h
10h
40h
40h
08h
16h
7Ch
F0h
21h
All other registers are set to 00h. The Subcarrier Frequency Registers 4Ch–4Fh
will be needed to generate the correct color burst signal.
For PAL Black Bar Pattern Output on DAC A, the same set-
tings in Table XXX are used except those listed in Table XXXI.
Table XXXI. PAL Black Bar Pattern Output on DAC A
Subaddress
Register Setting
40h
4Ch
4Dh
4Eh
4Fh
11h
CBh
8Ah
09h
2Ah
Table XXXII. 525 p Hatch Pattern on DAC D
Subaddress
Register Setting
00h
01h
02h
10h
11h
16h
17h
18h
12h
10h
20h
40h
05h
A0h
80h
80h
All other registers are set to 00h.
For a 625 p Hatch Pattern on DAC D, the same settings in
Table XXXII are used except for Subaddress 10h, which has a
register setting of 50h.
Table XXXIII. 525 p Field Pattern
*
Subaddress
Register Setting
00h
01h
02h
10h
11h
16h
17h
18h
12h
10h
20h
40h
0Dh
A0h
80h
80h
All other registers are set to 00h.
*
See Figure 90.
For a 625 p Field Pattern on DAC D, the same settings in
Table XXXIII are used except for Subaddress 10h, which has a
register setting of 50h.
For a 525 p Black Bar Pattern Output on DAC D, the same
settings in Table XXXIII are used except for Subaddresses 02h,
which has a register setting of 24h.
For a 625 p Black Bar Pattern Output on DAC D, the same
settings in Table XXXIII are used except for Subaddresses 02h
and 10h, which have register settings of 24h and 50h, respec-
tively.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| ADV7301AKST | 功能描述:IC DAC VIDEO HDTV 6-12BIT 64LQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV73025702 | 制造商:LG Corporation 功能描述:Frame Assembly |
| ADV73025801 | 制造商:LG Corporation 功能描述:Frame Assembly |
| ADV73025809 | 制造商:LG Corporation 功能描述:Frame Assembly |
| ADV7302A | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat SD, Progressive Scan/HDTV Video Encoder with Six 11-Bit DACs |
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