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參數(shù)資料
| 型號(hào)： | ADV7301A |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat SD, Progressive Scan/HDTV Video Encoder with Six NSV⑩ 12-Bit DACs |
| 中文描述： | 多格式統(tǒng)計(jì)，逐行掃描/ HDTV視頻編碼器與六噪聲整形⑩12位DAC |
| 文件頁數(shù)： | 54/68頁 |
| 文件大小： | 1544K |
| 代理商： | ADV7301A |
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REV. A
–54–
ADV7300A/ADV7301A
Appendix C
SD CLOSED CAPTIONING
[Subaddresses 51h–54h]
The ADV7300A/ADV7301A supports closed captioning con-
forming to the standard television synchronizing waveform for
color transmission. Closed captioning is transmitted during the
blanked active line time of Line 21 of the odd fields and Line
284 of the even fields.
Closed captioning consists of a seven cycle sinusoidal burst that
is frequency and phase-locked to the caption data. After the
clock run-in signal, the blanking level is held for 2 data bits and
is followed by a Logic Level “1” start bit. Sixteen bits of data
follow the start bit. These consist of two 8-bit bytes, 7 data bits,
and 1 odd parity bit. The data for these bytes is stored in the
SD Closed Captioning Registers [Addresses 53h–54h].
The ADV7300A/ADV7301A also supports the extended closed
captioning operation that is active during even fields and is
encoded on Line 284. The data for this operation is stored in
the SD Closed Captioning Registers [Addresses 51h–52h].
All clock run-in signals and timing to support closed captioning on
Lines 21 and 284 are generated automatically by the ADV7300A/
ADV7301A. All pixels inputs are ignored during Lines 21 and 284 if
closed captioning is enabled.
FCC Code of Federal Regulations (CFR) 47, Section 15.119
and EIA608 describe the closed captioning information for
Lines 21 and 284.
The ADV7300A/ADV7301A uses a single buffering method.
This means that the closed captioning buffer is only 1 byte
deep; therefore, there will be no frame delay in outputting the
closed captioning data unlike other 2-byte deep buffering
systems. The data must be loaded one line before (Line 20 or
Line 283) it is output on Line 21 and Line 284. A typical
implementation of this method is to use
VSYNC
to interrupt a
microprocessor that in turn will load the new data (2 bytes)
every field. If no new data is required for transmission, “0”
must be inserted in both data registers; this is called nulling. It
is also important to load “control codes,” all of which are
double bytes on Line 21, or a TV will not recognize them. If
there is a message like “Hello World” that has an odd number
of characters, it is important to pad it out to even to get the
“end of caption” 2-byte control code to land in the same field.
S
T
A
R
T
P
A
R
I
T
Y
P
A
R
I
T
Y
D0–D6
D0–D6
10.5 0.25 s
12.91 s
7 CYCLES OF
0.5035MHz
CLOCK RUN-IN
REFERENCE COLOR BURST
(9 CYCLES)
FREQUENCY = F
= 3.579545MHz
AMPLITUDE = 40 IRE
10.003 s
50 IRE
40 IRE
27.382 s
33.764 s
BYTE 1
BYTE 0
TWO 7-BIT + PARITY
ASCII CHARACTERS
(DATA)
Figure 83. Closed Captioning Waveform, NTSC
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| ADV7301AKST | 功能描述:IC DAC VIDEO HDTV 6-12BIT 64LQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV73025702 | 制造商:LG Corporation 功能描述:Frame Assembly |
| ADV73025801 | 制造商:LG Corporation 功能描述:Frame Assembly |
| ADV73025809 | 制造商:LG Corporation 功能描述:Frame Assembly |
| ADV7302A | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat SD, Progressive Scan/HDTV Video Encoder with Six 11-Bit DACs |
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