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參數(shù)資料
| 型號(hào)： | ADV7195KST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs and 10-Bit Data Input |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP52 |
| 封裝： | PLASTIC, MQFP-52 |
| 文件頁(yè)數(shù)： | 29/36頁(yè) |
| 文件大小： | 499K |
| 代理商： | ADV7195KST |
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REV. 0
ADV7195
–29–
Color Output Swap (MR53)
By default DAC B is configured as the Pr output and DAC C as
the Pb output. In setting this bit to “1,” the DAC outputs can
be swapped around so that DAC B outputs Pb and DAC C out-
puts Pr. Table X demonstrates this in more detail.
Reserved (MR54–MR57)
A “0” must be written to these bits.
Table X. Relationship Between Input Pixel Port, MR53
and DAC B, DAC C Outputs
In 4:4:4 Input Mode
Color Data
Input on Pins
Analog Output
Signal
MR53
Cr9–0
Cb/Cr9–0
Cr9–0
Cb/Cr9–0
0
0
1
1
DAC B
DAC C
DAC C
DAC B
In 4:2:2 Input Mode
Color Data
Input on Pins
Analog Output
Signal
MR53
Cr9–0
Cb/Cr9–0
Cb/Cr9–0
0 or 1
0
1
Not Operational
DAC C (Pb)
DAC C (Pr)
MR47
MR46
MR45
MR44
MR43
MR42
MR41
MR40
MR47
–
MR41
MR40
TIMING RESET
ZERO MUST BE
WRITTEN TO
THESE BITS
Figure 55. Mode Register 4
MR57
MR56
MR55
MR54
MR53
MR52
MR51
MR50
0
1
DAC B = PR
DAC C = R
MR53
COLOR OUTPUT SWAP
0
1
DISABLE
ENABLE
MR51
RGB MODE
0
1
DISABLE
ENABLE
MR52
SYNC ON PrPb
MR50
RESERVED FOR
REVISION CODE
MR57
–
MR54
ZERO MUST
BE WRITTEN
TO THESE BITS
Figure 56. Mode Register 5
MODE REGISTER 4
MR4 (MR47–MR40)
(Address (SR4–SR0) = 04H)
Figure 55 shows the various operations under the control of
Mode Register 4.
MR4 BIT DESCRIPTION
Timing Reset (MR40)
Toggling MR40 from low to high and low again resets the inter-
nal horizontal and vertical timing counters.
Reserved (MR41–MR47)
A “0” must be written to these bits.
MODE REGISTER 5
MR5 (MR57–MR50)
(Address (SR4–SR0) = 05H)
Figure 56 shows the various operations under the control of
Mode Register 5.
MR5 BIT DESCRIPTION
Reserved (MR50)
This bit is reserved for the revision code.
RGB Mode (MR51)
When RGB mode is enabled (MR51 = “1”), the ADV7195
accepts unsigned binary RGB data at its input port. This control
is also available in Async Timing Mode.
Sync on PrPb (MR52)
By default the color component output signals Pr, Pb do not con-
tain any horizontal sync pulses. If required, they can be inserted
when MR52 = “1.” This control is not available in RGB mode.
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| ADV7196 | Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs, 10-Bit Data Input, and Macrovision |
| ADV7196A | Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs, 10-Bit Data Input, and Macrovision |
| ADV7196AKS | Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs, 10-Bit Data Input, and Macrovision |
| ADV7197 | Multiformat HDTV Encoder with Three 11-Bit DACs |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7195KSZ | 制造商:Analog Devices 功能描述:Video Encoder 3DAC 11-Bit 52-Pin MQFP |
| ADV7196 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs, 10-Bit Data Input, and Macrovision |
| ADV7196A | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs, 10-Bit Data Input, and Macrovision |
| ADV7196AKS | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs, 10-Bit Data Input, and Macrovision |
| ADV7197 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat HDTV Encoder with Three 11-Bit DACs |
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