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參數(shù)資料
| 型號： | ADV7194KSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/69頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ENCODER VIDEO EXT-10 80-LQFP |
| 標準包裝： | 1 |
| 類型： | 視頻編碼器 |
| 應用： | DVD，視頻，多媒體 |
| 電壓 - 電源，模擬： | 3.3 V ~ 5 V |
| 電壓 - 電源，數(shù)字： | 3.3 V ~ 5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-LQFP |
| 供應商設備封裝： | 80-LQFP（14x14） |
| 包裝： | 托盤 |
| 產品目錄頁面： | 788 (CN2011-ZH PDF) |
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ADV7194
–18–
REV. A
UNDERSHOOT LIMITER
A limiter is placed after the digital lters. This prevents any
synchronization problems for TVs. The level of undershoot is
programmable between –1.5 IRE, –6 IRE, –11 IRE when oper-
ating in 4
× Oversampling Mode. In 2× Oversampling Mode the
limits are –7.5 IRE and 0 IRE. (Mode Register 9 and Timing
Register 0.)
DIGITAL NOISE REDUCTION
DNR is applied to the Y data only. A lter block selects the
high frequency, low-amplitude components of the incoming
signal (DNR Input Select). The absolute value of the lter output
is compared to a programmable threshold value (DNR Thresh-
old Control). There are two DNR modes available: DNR Mode
and DNR Sharpness Mode.
In DNR Mode, if the absolute value of the lter output is smaller
than the threshold, it is assumed to be noise. A programmable
amount (Coring Gain Control) of this noise signal will be sub-
tracted from the original signal.
In DNR Sharpness Mode, if the absolute value of the lter output
is less than the programmed threshold, it is assumed to be noise,
as before. Otherwise, if the level exceeds the threshold, now
being identied as a valid signal, a fraction of the signal (Coring
Gain Control) will be added to the original signal in order to boost
high frequency components and to sharpen the video image.
In MPEG systems it is common to process the video informa-
tion in blocks of 8
× 8 pixels for MPEG2 systems, or 16 × 16
pixels for MPEG1 systems (Block Size Control). DNR can be
applied to the resulting block transition areas that are known to
contain noise. Generally the block transition area contains two
pixels. It is possible to dene this area to contain four pixels
(Border Area Control).
It is also possible to compensate for variable block positioning or
differences in YCrCb pixel timing with the use of the Block Offset
Control. (Mode Register 8, DNR Registers 0–2.)
DOUBLE BUFFERING
Double buffering can be enabled or disabled on the following
registers: Closed Captioning Registers, Brightness Control
Register, V-Scale Register, U-Scale Register, Contrast Control
Register, Hue Adjust Register, and the Gamma Curve Select
bit. These registers are updated once per eld on the falling
edge of the
VSYNC signal. Double Buffering improves the over-
all performance of the ADV7194, since modications to register
settings will not be made during active video, but take effect on
the start of the active video. (Mode Register 8.)
GAMMA CORRECTION CONTROL
Gamma correction may be performed on the luma data. The
user has the choice to use either of two different gamma curves,
A or B. At any one time one of these curves is operational if
gamma correction is enabled. Gamma correction allows the
mapping of the luma data to a user-dened function. (Mode
Register 8, Gamma Correction Registers 0–13.)
NTSC PEDESTAL CONTROL
In NTSC mode it is possible to have the pedestal signal gener-
ated on the output video signal. (Mode Register 2.)
POWER-ON
RESET
After power-up, it is necessary to execute a
RESET operation.
A reset occurs on the falling edge of a high-to-low transition on
the
RESET pin. This initializes the pixel port such that the data
on the pixel inputs pins is ignored. See Appendix 8 for the regis-
ter settings after
RESET is applied.
PROGRESSIVE SCAN INPUT
It is possible to input data to the ADV7194 in progressive scan
format. For this purpose the input pins Y0/P10–Y9/P19, Cr0–Cr9,
Cb0–Cb9 accept 10-bit Y data, 10-bit Cb data and 10-bit Cr
data. The data is clocked into the part at 27 MHz. The data
is then ltered and sinc corrected in an 2
× Interpolation lter
and then output to three video DACs at 54 MHz (to interface to
a progressive scan monitor).
FREQUENCY – MHz
0
030
5
AMPLITUDE
–
dB
10
15
20
25
–10
–20
–30
–50
–60
–40
–70
Figure 32. Plot of the Interpolation Filter for the Y Data
FREQUENCY – MHz
0
030
5
AMPLITUDE
–
dB
10
15
20
25
–10
–20
–30
–50
–60
–40
–70
Figure 33. Plot of the Interpolation Filter for the CrCb Data
It is assumed that there is no color space conversion or any other
such operation to be performed on the incoming data. Thus if
these DAC outputs are to drive a TV, all relevant timing and
synchronization data should be contained in the incoming digital
Y data. An FPGA can be used to achieve this.
The block diagram below shows a possible conguration for
progressive scan mode using the ADV7194.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7194KSTZ | 制造商:Analog Devices 功能描述:TV / Video IC |
| ADV7195 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs and 10-Bit Data Input |
| ADV7195KS | 制造商:Analog Devices 功能描述:Video Encoder 3DAC 11-Bit 52-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:MULTI-FORMAT VID+PROGSCAN/HDTV ENCODERIC - Bulk |
| ADV7195KST | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs and 10-Bit Data Input |
| ADV7195KSZ | 制造商:Analog Devices 功能描述:Video Encoder 3DAC 11-Bit 52-Pin MQFP |
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