參數(shù)資料
型號(hào): ADV7194
廠商: Analog Devices, Inc.
英文描述: Professional Extended-10⑩ Video Encoder with 54 MHz Oversampling
中文描述: 專業(yè)擴(kuò)展- 10⑩視頻編碼器,54兆赫采樣
文件頁(yè)數(shù): 44/69頁(yè)
文件大?。?/td> 647K
代理商: ADV7194
ADV7194
–44–
REV. 0
BRIGHTNESS DETECT REGISTER
(Address (SR5–SR0) = 34H)
The Brightness Detect Register is an 8-bit-wide register used only
to read back data in order to monitor the brightness/darkness of
the incoming video data on a
fi
eld-by-
fi
eld basis. The brightness
information is read from the I
2
C and based on this information,
the color controls or the gamma correction controls may be
adjusted.
The luma data is monitored in the active video area only. The
average brightness I
2
C register is updated on the falling edge of
every
VSYNC
signal.
OUTPUT CLOCK REGISTER (OCR9–0)
(Address (SR4–SR0) = 35H)
The Output Clock Register is an 8-bit-wide register. Figure 93
shows the various operations under the control of this register.
OCR07
OCR06
OCR05
OCR04
OCR03
OCR02
OCR01
OCR00
OCR07
ZERO MUST BE
WRITTEN TO
THIS BIT
CLKOUT
PIN CONTROL
OCR01
0
1
ENSABLED
DISABLED
OCR06
OCR04
ONE MUST BE
WRITTEN TO
THESE BITS
OCR03
OCR02
ZERO MUST BE
WRITTEN TO
THESE BITS
OCR00
ZERO MUST BE
WRITTEN TO
THIS BIT
Figure 93. Mode Register 10 (MR10)
OCR BIT DESCRIPTION
Reserved (OCR00)
A Logic 0 must be written to this bit.
CLKOUT Pin Control (OCR01)
This bit enables the CLKOUT pin when set to 1 and, there-
fore, outputs a 54 MHz clock generated by the internal PLL.
The PLL and 4
×
Oversampling have to be enabled for this con-
trol to take effect, (MR61 = 0; MR16 = 1).
Reserved (OCR02–OCR03)
A Logic 0 must be written to these bits.
Reserved (OCR04–OCR06)
A Logic 1 must be written to these bits.
Reserved (OCR07)
A Logic 0 must be written to this bit.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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