參數(shù)資料
型號(hào)： ADV7171KSZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 16/64頁(yè)
文件大?。?/td> 0K
描述： IC DAC VIDEO ENC NTSC 44-MQFP
產(chǎn)品變化通告： Product Discontinuance 27/Oct/2011
標(biāo)準(zhǔn)包裝： 800
類型： 視頻編碼器
應(yīng)用： 機(jī)頂盒，視頻播放器
電壓 - 電源，模擬： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
封裝/外殼： 44-QFP
供應(yīng)商設(shè)備封裝： 44-MQFP（10x10）
包裝： 帶卷 (TR)
ADV7170/ADV7171
Rev. C | Page 23 of 64
Mode 1: Master Option HSYNC, BLANK, FIELD
(Timing Register 0 TR0 = X X X X X 0 1 1)
In this mode the ADV7170/ADV7171 can generate horizontal SYNC and odd/even FIELD signals. A transition of the FIELD input when
HSYNC is low indicates a new frame, that is, vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, the
ADV7170/ADV7171 automatically blank all normally blank lines as per CCIR-624. Pixel data is latched on the rising clock edge following
the timing signal transitions. Mode 1 is shown in
(NTSC) and
(PAL).
illustrates the
HSYNC, BLANK, and
FIELD for an odd or even field transition relative to the pixel data.
FIELD
PIXEL
DATA
PAL = 12
× CLOCK/2
NTSC = 16
× CLOCK/2
PAL = 132
× CLOCK/2
NTSC = 122
× CLOCK/2
Cb
Y
Cr
Y
HSYNC
BLANK
00221-026
Figure 26. Timing Mode 1 Odd/Even Field Transitions Master/Slave
Mode 2: Slave Option HSYNC, VSYNC, BLANK
(Timing Register 0 TR0 = X X X X X 1 0 0)
In this mode the ADV7170/ADV7171 accept horizontal and vertical SYNC signals. A coincident low transition of both HSYNC and
VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The
BLANK signal is optional. When the BLANK input is disabled, the ADV7170/ADV7171 automatically blank all normally blank lines as
per CCIR-624. Mode 2 is illustrated in
(NTSC) and
(PAL).
522
523
524
525
12
34
5
67
8
9
10
11
20
21
22
DISPLAY
ODD FIELD
EVEN FIELD
HSYNC
BLANK
VSYNC
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
ODD FIELD
EVEN FIELD
DISPLAY
HSYNC
BLANK
VSYNC
VERTICAL BLANK
00221-027
VERTICAL BLANK
Figure 27. Timing Mode 2 (NTSC)
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