參數(shù)資料
型號: ADV7150LS170
廠商: ANALOG DEVICES INC
元件分類: 顯示控制器
英文描述: CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC
中文描述: PALETTE-DAC DSPL CTLR, PQFP160
封裝: POWER, PLASTIC, QFP-160
文件頁數(shù): 27/36頁
文件大小: 447K
代理商: ADV7150LS170
ADV7150
–27–
REV. A
Digital Signal Interconnect
T he digital inputs to the ADV7150 should be isolated as much
as possible from the analog outputs and other analog circuitry.
Also, these input signals should not overlay the analog power
plane.
Due to the high clock rates involved, long clock lines to the
ADV7150 should be avoided to reduce noise pickup.
Any active termination resistors for the digital inputs should be
connected to the regular PCB power plane (V
CC
), and not the
analog power plane.
Analog Signal Interconnect
T he ADV7150 should be located as close as possible to the out-
put connectors to minimize noise pick-up and reflections due to
impedance mismatch.
T he video output signals should overlay the ground plane, and
not the analog power plane, to maximize the high frequency
power supply rejection.
Digital Inputs, especially Pixel Data Inputs and clocking signals
(CLOCK , LOADOUT , LOADIN, etc.) should never overlay
any of the analog signal circuitry and should be kept as far away
as possible.
For best performance, the analog outputs (IOR, IOG, IOB)
should each have a 75
load resistor connected to GND.
T hese resistors should be placed as close as possible to the
ADV7150 so as to minimize reflections. Normally, the differen-
tial analog outputs (
IOR
,
IOG
,
IO
B) are connected directly to
GND. In some applications, improvements in performance are
achieved by terminating these differential outputs with a resis-
tive load similar in value to the video load. For a doubly termi-
nated 75
load, this means that
IOR
,
IOG
,
IOB
are each
terminated with 37.5
resistors.
APPE NDIX 2
T Y PICAL FRAME BUFFE R INT E RFACE
CLOCK
ADV7150
CLOCK
LOADOUT
PRGCKOUT
LOADIN
SCKOUT
SCKIN
BLANK
LATCH
ENABLE
SYNC
ECL
TO
TTL
DIVIDE BY N
(
÷
N)
VRAM
(BANK A)
VRAM
(BANK B)
FRAME
BUFFER/
VIDEO
MEMORY
MULTIPLEXER
24
TO
PALETTE/RAM
& DAC
24
24
24
24
BLANK
SYNC
CLOCK
GRAPHICS
PROCESSOR/
CONTROLLER
VRAM
(BANK C)
24
24
VRAM
(BANK D)
24
24
33MHz
33MHz
33MHz
33MHz
DIVIDE BY M
(
÷
M)
CLOCK
GENERATOR
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