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參數(shù)資料
| 型號： | ADV7150LS110 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顯示控制器 |
| 英文描述： | CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC |
| 中文描述： | PALETTE-DAC DSPL CTLR, PQFP160 |
| 封裝： | POWER, PLASTIC, QFP-160 |
| 文件頁數(shù)： | 23/36頁 |
| 文件大?。?/td> | 447K |
| 代理商： | ADV7150LS110 |
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ADV7150
–23–
REV. A
COMMAND RE GIST E R 3 (CR3)
(Address Reg (A7–A0) = 07H)
T his register contains a number of control bits as shown in the
diagram. CR3 is a 10-bit wide register. However for program-
ming purposes, it may be considered as an 8-bit wide register
(CR38 and CR39 are both reserved).
T he diagram shows the various operations under the control of
CR3. T his register can be read from as well written to. In read
mode, CR38 and CR39 are both returned as zeros.
COMMAND RE GIST E R 3-BIT DE SCRIPT ION
PRGCK OUT Frequency Control (CR31–CR30)
T hese bits specify the output frequency of the PRGCK OUT
output. PRGCK OUT is a divided down version of the pixel
CLOCK .
BLANK
Pipeline Delay Control (CR35–CR32)
T hese bits specify the additional pipeline delay that can be
added to the
BLANK
function, relative to the overall device
pipeline delay (t
PD
). As the
BLANK
control normally enters the
video DAC from a shorter pipeline than the video pixel data,
this control is useful in deskewing the pipeline differential.
Pixel Multiplex Control (CR37–CR36)
T hese bits specify the device’s multiplex mode. It, therefore,
also determines the frequency of the LOADOUT signal.
LOADOUT is a divided down version of the pixel CLOCK .
Revision Register
(Address Reg (A7–A0) = 0BH)
T his register is a read only register containing the revision of
silicon.
CR39
CR38
CR37
CR36
CR35
CR34
CR32
CR31
CR30
CR33
*THESE BITS ARE READ-
ONLY RESERVED BITS.
A READ CYCLE WILL
RETURN ZEROS "00."
PRGCKOUT FREQUENCY
CONTROL
CR31 CR30
0
0
1
1
0
1
0
1
CLOCK
÷
4
CLOCK
÷
8
CLOCK
÷
16
CLOCK
÷
32
RESERVED*
PIXEL MULTIPLEX CONTROL
CR37 CR36
0
0
1
1
0
1
0
1
1:1 MUXING: LOADOUT = CLOCK
÷
1
2:1 MUXING LOADOUT = CLOCK
÷
2
RESERVED
4:1 MUXING :LOADOUT = CLOCK
÷
4
EXTRA BLANK PIPELINE DELAY CONTROL
(ADDS TO PIXEL PIPELINE DELAY; tPD)
CR35 CR34 CR33 CR32
0
0
0
1
0
1
0
1
0
0
1
1
0
0
0
1
t
PD
t
PD
+ 1 x LOADOUT
t
PD
+ 2 x LOADOUT
t
PD
+ 15 x LOADOUT
·
·
·
·
·
·
·
·
·
·
Command Register 3 (CR3) (CR39–CR30)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADV7150LS135 | CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC |
| ADV7150LS170 | CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC |
| ADV7150LS220 | CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC |
| ADV7183 | Video Decoder with 9-Bit ADC(帶9位A/D轉(zhuǎn)換器和自適應(yīng)梳狀濾波器視頻譯碼器) |
| ADV7184 | Multiformat SDTV Video Decoder with Fast Switch Overlay Support |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7150LS135 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ADV7150LS170 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ADV7150LS220 | 制造商:Analog Devices 功能描述: |
| adv7150ls85 | 制造商:Rochester Electronics LLC 功能描述:220MHZ 3X10 BIT VIDEO DAC - Bulk 制造商:Analog Devices 功能描述: |
| ADV7151 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 220 MHz Pseudo-Color Graphics Triple 10-Bit Video RAM-DAC |
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