參數(shù)資料
型號(hào)： ADV601LCJSTZRL
廠商： Analog Devices Inc
文件頁數(shù)： 35/44頁
文件大?。?/td> 0K
描述： IC CODEC VIDEO DSP/SRL 120LQFP
標(biāo)準(zhǔn)包裝： 1,000
類型： 視頻編解碼器
數(shù)據(jù)接口： DSP，串行
分辨率（位）： 8 b
三角積分調(diào)變： 無
電壓 - 電源，模擬： 4.5 V ~ 5.5 V
電壓 - 電源，數(shù)字： 4.5 V ~ 5.5 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 120-LQFP
供應(yīng)商設(shè)備封裝： 120-LQFP（14x14）
包裝： 帶卷 (TR)
ADV601LC
–40–
REV. 0
Host Interface (Compressed Data) Register Timing
The diagrams in this section show transfer timing for host read and write transfers to the ADV601LC’s Compressed Data register.
Accesses to the Compressed Data register are faster than access timing for the Indirect Address, Indirect Register Data, and Interrupt
Mask/Status registers. For information on access timing for the other registers, see the Host Interface (Indirect Address, Indirect
Register Data, and Interrupt Mask/Status) Register Timing section. Also note that as long as your system observes the RD or WR
signal assertion timing, your system does NOT have to wait for the ACK signal between new compressed data addresses.
Table XXIX. Host (Compressed Data) Read Timing Parameters
Parameter
Description
Min
Max
Unit
tRD_CD_RDC
RD Signal, Compressed Data Direct Register, Read Cycle Time
28
N/A
ns
tRD_CD_PWA
RD Signal, Compressed Data Direct Register, Pulsewidth Asserted
10
N/A
ns
tRD_CD_PWD
RD Signal, Compressed Data Direct Register, Pulsewidth Deasserted
10
N/A
ns
tADR_CD_RDS
ADR Bus, Compressed Data Direct Register, Read Setup
2
N/A
ns
tADR_CD_RDH
ADR Bus, Compressed Data Direct Register, Read Hold (at 27 MHz VCLK)
2
N/A
ns
tDATA_CD_RDD
DATA Bus, Compressed Data Direct Register, Read Delay
N/A
10
ns
tDATA_CD_RDOH
DATA Bus, Compressed Data Direct Register, Read Output Hold
18
N/A
ns
tACK_CD_RDD
ACK Signal, Compressed Data Direct Register, Read Delay
N/A
18
ns
tACK_CD_RDOH
ACK Signal, Compressed Data Direct Register, Read Output Hold
9
N/A
ns
(I) ADR,
BE, CS
(I)
RD
(O) DATA
(O)
ACK
VALID
t
ADR_CD_RDS
t
DATA_CD_RDD
t
ACK_CD_RDD
t
ACK_CD_RDOH
t
DATA_CD_RDOH
t
ADR_CD_RDH
t
RD_CD_RDC
t
RD_CD_PWA
t
RD_CD_PWD
Figure 30. Host (Compressed Data) Read Transfer Timing
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參數(shù)描述
ADV601LC-VIDEOPIPE 制造商:Analog Devices 功能描述:TOOLS:DEVELOPMENT BOARDS H/W 制造商:Analog Devices 功能描述:EVALUATION BOARD ((NS))
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ADV611JSTZ 功能描述:IC CCTV DGTL VIDEO CODEC 120LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR)
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