參數(shù)資料
型號: ADV601LCJSTZRL
廠商: Analog Devices Inc
文件頁數(shù): 22/44頁
文件大?。?/td> 0K
描述: IC CODEC VIDEO DSP/SRL 120LQFP
標準包裝: 1,000
類型: 視頻編解碼器
數(shù)據(jù)接口: DSP,串行
分辨率(位): 8 b
三角積分調(diào)變:
電壓 - 電源,模擬: 4.5 V ~ 5.5 V
電壓 - 電源,數(shù)字: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 120-LQFP
供應商設備封裝: 120-LQFP(14x14)
包裝: 帶卷 (TR)
ADV601LC
–29–
REV. 0
ADR1
ADR2
DATA0–7
DATA8-15
ADR0
CLKIN
FLIN2
FLIN0
ADR0
ADR1
DQ0–DQ7
DQ8–DQ15
DQ16–DQ23
DQ24–DQ31
STATS_R
LCODE
A0–A8
D0–D15
A0–A8
DQ1–DQ16
THE ADSP-21csp01 INTERNAL CLOCK RATE
DOUBLE THE INPUT CLOCK
*THE INPUT CLOCK RATE = 1/2 OF THE INTERNAL
CLOCK RATE, RANGING FROM 12 TO 21MHz
ADV601LC
ADSP-21csp01
DRAM
(256K
16-BIT)
VCLKO*
TOSHIBA TC514265DJ/DZ/DFT-60
NEC
PD424210ALE-60
NEC
PD42S4210ALE-60
HITACHI
HM514265CJ-60
ANY DRAM USED WITH THE ADV601LC
MUST MEET THE MINIMUM SPECIFICATIONS
OUTLINED FOR THE HYPER MODE DRAMS
LISTED
FIFO_SRQ
FIFO_STP
FIFO_ERR
IRQ0
FLIN1
IOMS
RD
WR
BE2–BE3
CS
RD
WR
HIRQ
ACK
RAS
CAS
WE
RAS
CAS
OE
WEL
WEH
IOACK
VCLK
VDATA [0–7]
LLC
XTAL
SAA7111
COMPOSITE VIDEO INPUT
Y[0–7]
BE0–BE1
27MHz PAL OR NTSC
24.576MHz
XTAL
Figure 14. Alternate Standalone Application Design
Using the ADV601LC In Standalone Applications
Figure 14 shows the ADV601LC in a noncomputer based appli-
cations. Here, an ADSP-21csp01 digital signal processor pro-
vides Host control and BW calculation services. Note that all
control and BW operations occur over the host interface in this
design.
Connecting the ADV601LC to Popular Video Decoders and
Encoders
The following circuits are recommendations only. Analog
Devices has not actually built or tested these circuits.
Using the Philips SAA7111 Video Decoder
The SAA7111 example circuit, which appears in Figure 15, is
used in this configuration on the ADV601LC Video Lab dem-
onstration board.
XTAL
(CCIR-656 MODE)
SAA7111
Y(0:7)
LLC
XTAL
VCLK
VDATA (0:7)
ADV601LC
Figure 15. ADV601LC and SAA7111 Example Interfac-
ing Block Diagram
Using the Analog Devices ADV7175 Video Encoder
Because the ADV7175 has a CCIR-656 interface, it connects
directly with the ADV601LC without “glue” logic. Note that
the ADV7175 can only be used at CCIR-601 sampling rates.
The ADV7175 example circuit, which appears in Figure 16, is
used in this configuration on the ADV601LC Video Lab dem-
onstration board.
(MODE 0 & SLAVE MODE)
(CCIR-656 MODE)
XTAL
10k
150
VCLK
XTAL
ADV601LC
VCLKO
CLOCK
P7–P0
ADV7175
BLANK
ALSB
VDATA (7:0)
Figure 16. ADV601LC and ADV7175 Example Interfac-
ing Block Diagram
Using the Raytheon TMC22173 Video Decoder
Raytheon has a whole family of video parts. Any member of the
family can be used. The user must select the part needed based
on the requirements of the application. Because the Raytheon
part does not include the A/Ds, an external A/D is necessary in
this design (or a pair of A/Ds for S video).
The part can be used in CCIR-656 (D1) mode for a zero con-
trol signal interface. Special attention must be paid to the video
output modes in order to get the right data to the right pins (see
the following diagram).
Note that the circuit in Figure 17 has not been built or tested.
MODE SET TO:
CDEC = 1
YUVT
= 1
F422
= X
TMC22153
Y(2:9)
CLOCK
XTAL
VCLK
VDATA (0:7)
ADV601LC
(CCIR656 & SLAVE MODE)
Figure 17. ADV601LC and TMC22153 Example CCIR-656
Mode Interface
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