參數(shù)資料
型號(hào)： ADV601LC
廠商： Analog Devices, Inc.
元件分類： 視頻Codec
英文描述： Ultralow Cost Video Codec
中文描述： 超低成本視頻編解碼器
文件頁(yè)數(shù)： 47/52頁(yè)
文件大?。?/td> 606K
代理商： ADV601LC
ADV601
–47–
REV. 0
Host Interface (Compressed Data) Register Timing
The diagrams in this section show transfer timing for host read and write transfers to the ADV601’s Compressed Data register. Ac-
cesses to the Compressed Data register are faster than access timing for the Indirect Address, Indirect Register Data, and Interrupt
Mask/Status registers. For information on access timing for the other registers, see the Host Interface (Indirect Address
,
Indirect
Regis
ter Data, and Interrupt Mask/Status) Register Timing section. Also note that as long as your system observes the
RD
or
WR
signal assertion timing, your system does
NOT
have to wait for the
ACK
signal between new compressed data addresses.
Table XXXV. Host (Compressed Data) Read Timing Parameters
Parameter
Description
Min
Max
Unit
t
RD_CD_RDC
t
RD_CD_PWA
t
RD_CD_PWD
t
ADR_CD_RDS
t
ADR_CD_RDH
t
DATA_CD_RDD
t
DATA_CD_RDOH
t
ACK_CD_RDD
t
ACK_CD_RDOH
RD
Signal, Compressed Data Direct Register, Read Cycle Time
RD
Signal, Compressed Data Direct Register, Pulse Width Asserted
RD
Signal, Compressed Data Direct Register, Pulse Width Deasserted
ADR Bus, Compressed Data Direct Register, Read Setup
ADR Bus, Compressed Data Direct Register, Read Hold (at 27 MHz VCLK)
DATA Bus, Compressed Data Direct Register, Read Delay
DATA Bus, Compressed Data Direct Register, Read Output Hold
ACK
Signal, Compressed Data Direct Register, Read Delay
ACK
Signal, Compressed Data Direct Register, Read Output Hold
28
10
10
2
2
N/A
18
N/A
9
N/A
N/A
N/A
N/A
N/A
10
N/A
18
N/A
ns
ns
ns
ns
ns
ns
ns
ns
ns
(I) ADR,
BE
,
CS
(I)
RD
(O) DATA
(O)
ACK
VALID
VALID
VALID
VALID
t
ADR_CD_RDS
t
DATA_CD_RDD
t
ACK_CD_RDD
t
ACK_CD_RDOH
t
DATA_CD_RDOH
t
ADR_CD_RDH
t
RD_CD_RDC
t
RD_CD_PWA
t
RD_CD_PWD
Figure 39. Host (Compressed Data) Read Transfer Timing
相關(guān)PDF資料
PDF描述
ADV601LCJST Ultralow Cost Video Codec
ADV7120KP30 CMOS 80 MHz, Triple 8-Bit Video DAC
ADV7120 CMOS 80 MHz, Triple 8-Bit Video DAC
ADV7120KP50 CMOS 80 MHz, Triple 8-Bit Video DAC
ADV7120KP80 CMOS 80 MHz, Triple 8-Bit Video DAC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADV601LCERAG1266B-0.5 制造商:Analog Devices 功能描述:
ADV601LCJST 制造商:Analog Devices 功能描述:Ultralow Cost Video Codec 120-Pin LQFP 制造商:Analog Devices 功能描述:IC VIDEO CODEC
ADV601LCJSTRL 制造商:Analog Devices 功能描述:Ultralow Cost Video Codec 120-Pin LQFP T/R
ADV601LCJSTZ 功能描述:IC CODEC VIDEO DSP/SRL 120LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR)
ADV601LCJSTZRL 功能描述:IC CODEC VIDEO DSP/SRL 120LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR)
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*