參數(shù)資料
型號(hào)： ADV601LC
廠商： Analog Devices, Inc.
元件分類： 視頻Codec
英文描述： Ultralow Cost Video Codec
中文描述： 超低成本視頻編解碼器
文件頁(yè)數(shù)： 13/52頁(yè)
文件大?。?/td> 606K
代理商： ADV601LC
ADV601
–13–
REV. 0
VIDEO AREA REGISTERS
The area defined by the HSTART, HEND, VSTART and VEND registers is the active area that the wavelet kernel processes. Video
data outside the active video area is set to minimum luminance and zero chrominance (black) by the ADV601. These registers allow
cropping of the input video during compression (encode only), but do not change the image size. Figure 10 shows how the video area
registers work together.
HSTART
0, 0
VSTART
VEND
HEND
ZERO
ZERO
ZERO
X, Y
ACTIVE VIDEO AREA
ZERO
ZERO
ZERO
ZERO
ZERO
MAX FOR SELECTED VIDEO MODE
Figure 10. Video Area and Video Area Registers
HSTART Register
Indirect (Write Only) Register Index 0x02
This register holds the setting for the horizontal start of the ADV601’s active video area. The value in this register is usually set to
zero, but in cases where you wish to crop incoming video it is possible to do so by changing HST.
[9:0]
Horizontal Start,
HST[9:0]
. 10-bit value defining the start of the active video region. (0 at reset)
[15:10] Reserved (always write zero)
HEND Register
Indirect (Write Only) Register Index 0x03
This register holds the setting for the horizontal end of the ADV601’s active video area. If the value is larger than the max size of the
selected video mode, the ADV601 uses the max size of the selected mode for HEND.
[9:0]
Horizontal End,
HEN[9:0]
.10-bit value defining the end of the active video region. (0x3FF at reset this value is larger than
the max size of the largest video mode)
[15:10] Reserved (always write zero)
VSTART Register
Indirect (Write Only) Register Index 0x04
This register holds the setting for the vertical start of the ADV601’s active video area. The value in this register is usually set to zero
unless you want to crop the active video.
To vertically crop video while encoding, program the VSTART and VEND registers with actual video line numbers, which differ for
each field. The VSTART and VEND contents must be updated on each field. Perform this updating as part of the field-by-field BW regis-
ter update process. To perform this dynamic update correctly, the update software must keep track of which field is being processed next.
[9:0]
Vertical Start,
VST[9:0]
. 10-bit value defining the starting line of the active video region, with line numbers from 1-to-625
in PAL and 1-to-525 in NTSC. (0 at reset)
[15:10] Reserved (always write zero)
VEND Register
Indirect (Write Only) Register Index 0x05
This register holds the setting for the vertical end of the ADV601’s active video area. If the value is larger than the max size of the
selected video mode, the ADV601 uses the max size of the selected mode for VEND.
To vertically crop video while encoding, program the VSTART and VEND registers with actual video line numbers, which differ for
each field. The VSTART and VEND contents must be updated on each field. Perform this updating as part of the field-by-field BW
register update process. To perform this dynamic update correctly, the update software must keep track of which field is being pro-
cessed next.
[9:0]
Vertical End,
VEN[9:0]
. 10-bit value defining the ending line of the active video region, with line numbers from 1-to-625
in PAL and 1-to-525 in NTSC. (0x3FF at reset—this value is larger than the max size of the largest video mode)
[15:10] Reserved (always write zero)
相關(guān)PDF資料
PDF描述
ADV601LCJST Ultralow Cost Video Codec
ADV7120KP30 CMOS 80 MHz, Triple 8-Bit Video DAC
ADV7120 CMOS 80 MHz, Triple 8-Bit Video DAC
ADV7120KP50 CMOS 80 MHz, Triple 8-Bit Video DAC
ADV7120KP80 CMOS 80 MHz, Triple 8-Bit Video DAC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADV601LCERAG1266B-0.5 制造商:Analog Devices 功能描述:
ADV601LCJST 制造商:Analog Devices 功能描述:Ultralow Cost Video Codec 120-Pin LQFP 制造商:Analog Devices 功能描述:IC VIDEO CODEC
ADV601LCJSTRL 制造商:Analog Devices 功能描述:Ultralow Cost Video Codec 120-Pin LQFP T/R
ADV601LCJSTZ 功能描述:IC CODEC VIDEO DSP/SRL 120LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR)
ADV601LCJSTZRL 功能描述:IC CODEC VIDEO DSP/SRL 120LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR)
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*