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參數(shù)資料
| 型號： | ADV3203ASWZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CROSSPOINT SWIT 32X16 176LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 功能： | 交叉點開關(guān) |
| 電路： | 1 x 32:16 |
| 電壓電源： | 單/雙電源 |
| 電壓 - 電源，單路/雙路(±)： | 5V，±2.5V，±3.3V |
| 電流 - 電源： | 200mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 176-LQFP |
| 供應(yīng)商設(shè)備封裝： | 176-LQFP-EP（24x24） |
| 包裝： | 托盤 |
ADV3202/ADV3203
Rev. 0 | Page 14 of 20
THEORY OF OPERATION
The ADV3202/ADV3203 are single-ended crosspoint arrays
with 16 outputs, each of which can be connected to any one
of 32 inputs.The 32 switchable input stages are connected to
each output buffer to form 32-to-1 multiplexers. There are 16 of
these multiplexers, each with its inputs wired in parallel, for a
total array of 512 stages forming a multicast-capable crosspoint
switch. In addition to connecting to any of the nominal inputs
(INxx), each output can also be connected to an associated OSD
input through an additional 2-to-1 multiplexer at each output.
This 2-to-1 multiplexer switches between the output of the 32-
to-1 multiplexer and the OSD input.
Each input to the ADV3202/ADV3203 is buffered by a receiver.
The purpose of this receiver is to provide overvoltage protection
for the input stages by limiting signal swing. In the ADV3202,
the output of the receiver is limited to ±1.2 V about VREF,
while in the ADV3203, the signal swing is limited to ±1.2 V
about midsupply. This receiver is configured as a voltage
feedback unity-gain amplifier. Excess loop gain bandwidth
product reduces the effect of the closed-loop gain on the
bandwidth of the device. In addition to a receiver, each input
also has a sync-tip clamp for use in ac-coupled applications.
This clamp is either enabled or disabled according to the 193rd
serial data bit. When enabled, the clamp forces the lowest video
voltage to the voltage on the VCLAMP pin. The VCLAMP pin
is common for the entire chip and needs to be driven with a low
impedance to avoid crosstalk.
x1
OUT00
VPOS
VNEG
FROM INPUT
STAGES
VPOS
VNEG
OSD00
OSDS00
9
07
52
6-
01
Figure 19. Conceptual Diagram of Single Output Channel, G = +1 (ADV3202)
Decoding logic for each output selects one (or none) of the
input stages to drive the output stage. The enabled input stage
drives the output stage, which is configured as a unity-gain
amplifier in the ADV3202 (see Figure 19). In the ADV3203, an
internal resistive feedback network and reference buffer provide
for a total output stage gain of +2 (see Figure 20). The input
voltage to the reference buffer is the VREF pin. This voltage is
common for the entire chip and needs to be driven with a low
impedance to avoid crosstalk.
OUT00
x1
VPOS
VNEG
FROM INPUT
STAGES
VPOS
VNEG
VREF
VPOS
VNEG
OSD00
OSDS00
2k
20
07
52
6-
0
Figure 20. Conceptual Diagram of Single Output Channel, G = +2 (ADV3203)
0
752
6-
0
21
IN00
VPOS
VNEG
VCLAMP
5A
TO INPUT
RECEIVER
OFF-CHIP
CAPACITOR
Figure 21. Conceptual Diagram of Sync-Tip Clamp in an
AC-Coupled Application
The output stage of the ADV3202/ADV3203 is designed for low
differential gain and phase error when driving composite video
signals. It also provides slew current for fast pulse response
when driving component video signals.
The outputs of the ADV3202/ADV3203 can be disabled to
minimize on-chip power dissipation. When disabled, a series of
internal amplifiers drive internal nodes such that a wideband
high impedance is presented at the disabled output, even while
the output bus is under large signal swings. (In the ADV3203,
there is 4 kΩ of resistance terminated to the VREF voltage by
the reference buffer). This high impedance allows multiple ICs
to be bussed together without additional buffering. Care must
be taken to reduce output capacitance, which results in more
overshoot and frequency domain peaking. In addition, when
the outputs are disabled and driven externally, the voltage
applied to them should not exceed the valid output swing range
for the ADV3202/ADV3203 to keep these internal amplifiers in
their linear range of operation. Applying excess voltage to the
disabled outputs can cause damage to the ADV3202/ADV3203
and should be avoided (see the Absolute Maximum Ratings
section for guidelines).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV3203-EVALZ | 功能描述:ADV3203 - Interface, Crosspoint Switch/Multiplexer Evaluation Board 制造商:analog devices inc. 系列:- 零件狀態(tài):有效 主要用途:接口，交叉點開關(guān)/多路復(fù)用器 嵌入式:- 使用的 IC/零件:ADV3203 主要屬性:32 x 16 視頻交叉點開關(guān) 輔助屬性:圖形用戶界面 所含物品:板，線纜 標(biāo)準(zhǔn)包裝:1 |
| ADV3205 | 制造商:AD 制造商全稱:Analog Devices 功能描述:60 MHz, G = +2, 16 × 16 |
| ADV3205-EVALZ | 制造商:Analog Devices 功能描述:ADV3025 SWITCH EVALUATION BOARD 制造商:Analog Devices 功能描述:ADV3025, SWITCH, EVALUATION BOARD |
| ADV3205JSTZ | 功能描述:IC CROSSPOINT SWIT 16X16 100LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 模擬開關(guān)，多路復(fù)用器，多路分解器 系列:- 應(yīng)用說明:Ultrasound Imaging Systems Application Note 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- 功能:開關(guān) 電路:單刀單擲 導(dǎo)通狀態(tài)電阻:48 歐姆 電壓電源:單電源 電壓 - 電源，單路/雙路(±):2.7 V ~ 5.5 V 電流 - 電源:5µA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應(yīng)商設(shè)備封裝:48-LQFP（7x7） 包裝:托盤 |
| ADV32121501 | 制造商:LG Corporation 功能描述:Frame Assembly |
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