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參數(shù)資料
| 型號： | ADV101* |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CMOS 80 MHz. Triple 8-Bit Video DAC |
| 中文描述： | 80兆赫的CMOS。三8位視頻DAC |
| 文件頁數(shù)： | 3/12頁 |
| 文件大小： | 187K |
ADV101
–3–
REV. B
Parameter
80 MHz Version
50 MHz Version
30 MHz Version
Units
Conditions/Comments
f
MAX
t
1
t
2
t
3
t
4
t
5
t
6
80
3
2
12.5
4
4
30
20
3
12
50
6
2
20
7
7
30
20
3
15
30
8
2
33.3
9
9
30
20
3
15
MHz max
ns min
ns min
ns min
ns min
ns min
ns max
ns typ
ns max
ns typ
Clock Rate
Data & Control Setup T ime
Data & Control Hold T ime
Clock Cycle T ime
Clock Pulse Width High T ime
Clock Pulse Width Low T ime
Analog Output Delay
t
7
t
83
Analog Output Rise/Fall T ime
Analog Output T ransition T ime
NOT ES
1
T T L input values are 0 to 3 volts, with input rise/fall times
≤
3 ns, measured between the 10% and 90% points. T iming reference points at 50% for inputs and out-
puts. See timing notes in Figure 1.
2
T emperature range (T
to T
): 0
°
C to +70
°
C.
3
Sample tested at +25
°
C to ensure compliance.
Specifications subject to change without notice.
TIMNGCHARACTERISTICS
1
(V
AA
= +5 V
6
5%; V
REF
= +1.235 V; R
L
= 37.5
V
, C
L
= 10 pF; R
SET
= 560
V
.
I
SYNC
connected to IOG. All Specifications T
MN
to T
MAX2
unless otherwse noted.)
CLOCK
DATA
ANALOG OUTPUTS
(IOR, IOG, IOB, I
SYNC
)
DIGITAL INPUTS
(R0–R7, G0–G7, B0–B7;
SYNC, BLANK,
REF WHITE)
t
4
t
5
t
3
t
1
t
2
t
6
t
8
t
7
NOTES
1. OUTPUT DELAY (
t
) MEASURED FROM THE 50% POINT OF THE RISING EDGE OF
CLOCK TO THE 50% POINT OF FULL-SCALE TRANSITION.
2. TRANSITION TIME (
t
) MEASURED FROM THE 50% POINT OF FULL-SCALE
TRANSITION TO WITHIN 2% OF THE FINAL OUTPUT VALUE.
3. OUTPUT RISE/FALL TIME (
t
7
) MEASURED BETWEEN THE 10% AND 90% POINTS
OF FULL TRANSITION.
Figure 1. Video Input/Output Timing
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