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參數(shù)資料
| 型號(hào)： | ADV101* |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CMOS 80 MHz. Triple 8-Bit Video DAC |
| 中文描述： | 80兆赫的CMOS。三8位視頻DAC |
| 文件頁(yè)數(shù)： | 11/12頁(yè) |
| 文件大?。?/td> | 187K |
ADV101
–11–
REV. B
Power Planes
T he PC board layout should have two distinct power planes,
one for analog circuitry and one for digital circuitry. T he analog
power plane should encompass the ADV101 (V
AA
) and all asso-
ciated analog circuitry. T his power plane should be connected
to the regular PCB power plane (V
CC
) at a single point through
a ferrite bead, as illustrated in Figure 8. T his bead should be lo-
cated within three inches of the ADV101.
T he PCB power plane should provide power to all digital logic
on the PC board, and the analog power plane should provide
power to all ADV101 power pins, voltage reference circuitry and
any output amplifiers.
T he PCB power and ground planes should not overlay portions
of the analog power plane. K eeping the PCB power and ground
planes from overlaying the analog power plane will contribute to
a reduction in plane-to-plane noise coupling.
Supply Decoupling
Noise on the analog power plane can be further reduced by the
use of multiple decoupling capacitors. (See Figure 8.)
Optimum performance is achieved by the use of 0.1
μ
F ceramic
capacitors. Each of the two groups of V
AA
should be individually
decoupled to ground. T his should be done by placing the ca-
pacitors as close as possible to the device with the capacitor
leads as short as possible, thus minimizing lead inductance.
It is important to note that while the ADV101 contains circuitry
to reject power supply noise, this rejection decreases with fre-
quency. If a high frequency switching power supply is used, the
designer should pay close attention to reducing power supply
noise. A dc power supply filter (Murata BNX 002) will provide
EMI suppression between the switching power supply and the
main PCB. Alternatively, consideration could be given to using
a three-terminal voltage regulator.
Digital Signal Interconnect
T he digital signal lines to the ADV101 should be isolated as
much as possible from the analog outputs and other analog cir-
cuitry. Digital signal lines should not overlay the analog power
plane.
Due to the high clock rates used, long clock lines to the
ADV101 should be avoided so as to minimize noise pickup.
Any active pull-up termination resistors for the digital inputs
should be connected to the regular PCB power plane (V
CC
), and
not the analog power plane.
Analog Signal Interconnect
T he ADV101 should be located as close as possible to the out-
put connectors thus minimizing noise pickup and reflections
due to impedance mismatch.
T he video output signals should overlay the ground plane, and
not the analog power plane, thereby maximizing the high fre-
quency power supply rejection.
For optimum performance, the analog outputs should each have
a source termination resistance to ground of 75
(doubly
terminated 75
configuration). T his termination resistance
should be as close as possible to the ADV101 so as to minimize
reflections.
Additional information on PCB design is available in an applica-
tion note entitled “Design and Layout of a Video Graphics Sys-
tem for Reduced EMI.” T his application note is available from
Analog Devices, publication number E1309–15–10/89.
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相關(guān)代理商/技術(shù)參數(shù) |
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| ADV101KN30 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
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| ADV101KN80 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ADV101KP30 | 制造商:Rochester Electronics LLC 功能描述:TRIPLE 8 BIT CMOS V.DAC - Bulk 制造商:Analog Devices 功能描述: |
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