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參數(shù)資料
| 型號(hào)： | ADUM3210ARZ-RL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO8 |
| 封裝： | ROHS COMPLIANT, MS-012AA, SOIC-8 |
| 文件頁(yè)數(shù)： | 9/20頁(yè) |
| 文件大?。?/td> | 690K |
| 代理商： | ADUM3210ARZ-RL7 |
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ADuM3210/ADuM3211
Rev. C | Page 17 of 20
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event were to occur during a transmitted
pulse (and had the worst-case polarity), it would reduce the
received pulse from >1.0 V to 0.75 V, which is still well above
the 0.5 V sensing threshold of the decoder.
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances away from the
ADuM321x transformers. Figure 14 expresses these allowable
current magnitudes as a function of frequency for selected
distances. As shown, the ADuM321x is immune and can be
affected only by extremely large currents operated at a high
frequency and very close to the component. For the 1 MHz
example, one would have to place a 0.5 kA current 5 mm away
from the ADuM321x to affect the operation of the component.
MAGNETIC FIELD FREQUENCY (Hz)
M
A
X
IM
U
M
AL
L
O
W
A
BL
E
C
URRE
NT
(
k
A)
1000
100
10
1
0.1
0.01
1k
10k
100M
100k
1M
10M
DISTANCE = 5mm
DISTANCE = 1m
DISTANCE = 100mm
06
86
6-
01
1
Figure 14. Maximum Allowable Current for Various
Current-to-ADuM3210/ADuM3211 Spacings
Note that at combinations of strong magnetic fields and high
frequencies, any loops formed by PCB traces may induce
sufficiently large error voltages to trigger the threshold of
succeeding circuitry. Care should be taken in the layout of
such traces to avoid this possibility.
POWER CONSUMPTION
The supply current at a given channel of the ADuM321x
isolator is a function of the supply voltage, channel data
rate, and channel output load.
For each input channel, the supply current is given by
IDDI = IDDI (Q)
f ≤ 0.5fr
IDDI = IDDI (D) × (2f – fr) + IDDI (Q)
f > 0.5fr
For each output channel, the supply current is given by
IDDO = IDDO (Q)
f ≤ 0.5fr
IDDO = (IDDO (D) + (0.5 × 103) × CLVDDO) × (2f – fr) + IDDO (Q)
f > 0.5fr
where:
IDDI (D), IDDO (D) are the input and output dynamic supply currents
per channel (mA/Mbps).
IDDI (Q), IDDO (Q) are the specified input and output quiescent
supply currents (mA).
CL is the output load capacitance (pF).
VDDO is the output supply voltage (V).
f is the input logic signal frequency (MHz, half of the input data
rate, NRZ signaling).
fr is the input stage refresh rate (Mbps).
To calculate the total IDD1 and IDD2 supply current, the supply
currents for each input and output channel corresponding to
IDD1 and IDD2 are calculated and totaled.
Figure 6 provides per-channel input supply currents as a function
supply currents as a function of data rate for an unloaded
output condition and for a 15 pF output condition, respectively.
current as a function of data rate for the ADuM3210 and
ADuM3211 channel configurations.
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