參數(shù)資料
型號: ADUC845
廠商: Analog Devices, Inc.
元件分類: ADC
英文描述: MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU
中文描述: MicroConverter的多通道ADC的24-/16-Bit與嵌入式62 kB閃存以及單周期控制器
文件頁數(shù): 28/108頁
文件大?。?/td> 1109K
代理商: ADUC845
ADuC845/ADuC847/ADuC848
This offset is removed by performing a running average of 2.
This average by 2 means that the settling time to any change in
programming of the ADC is twice the normal conversion time,
while an asynchronous step change on the analog input is not
fully reflected until the third subsequent output. See Figure 13.
Rev. A | Page 28 of 108
ADC
ADC
SETTLE
t
f
t
×
=
=
2
2
The allowable range for SF (chop enabled) is 13 to 255 with
a default of 69 (45H). The corresponding conversion rates,
rms and peak-to-peak noise performances are shown in
Table 10, Table 11, Table 12, and Table 13. The numbers are
typical and generated at a differential input voltage of 0 V
and a common-mode voltage of 2.5 V. Note that the con-
version time increases by 0.732 ms for each increment in SF.
SAMPLE 1
NO/INVALID
OUTPUT
SAMPLE 2
SAMPLE 3
SAMPLE 4
SAMPLE 5
SAMPLE 6
SAMPLE 1 + SAMPLE 2
2
VALID OUTPUT
SAMPLE 5 + SAMPLE 6
2
VALID OUTPUT
SAMPLE 2 + SAMPLE 3
2
VALID OUTPUT
SYNCHRONOUS CHANGE
(I.E. CHANNEL CHANGE)
SAMPLE 4 + SAMPLE 5
2
VALID OUTPUT
SAMPLE 3 + SAMPLE 4
2
NO OUTPUT
0
Figure 13. ADC Settling Time Following a Synchronous Change with
Chop Enabled
SAMPLE 1
NO OUTPUT
SAMPLE 2
SAMPLE 3
SAMPLE 4
SAMPLE 5
SAMPLE 6
SAMPLE 1 + SAMPLE 2
2
VALID OUTPUT
SAMPLE 5 + SAMPLE 6
2
VALID OUTPUT
SAMPLE 2 + SAMPLE 3
2
VALID OUTPUT
ASYNCHRONOUS CHANGE
(I.E. DISCONTINUOUS INPUT CHANGE)
SAMPLE 4 + SAMPLE 5
2
UNSETTLED OUTPUT
SAMPLE 3 + SAMPLE 4
2
UNSETTLED OUTPUT
0
Figure 14. ADC Settling Time Following an Asynchronous Change with
Chop Enabled
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