參數(shù)資料
型號(hào)： ADUC842BS62-5
廠商： ANALOG DEVICES INC
元件分類(lèi)： 微控制器/微處理器
英文描述： MicroConverter 12-Bit ADCs and DACs with Embedded High Speed 62-kB Flash MCU
中文描述： 8-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP52
封裝： PLASTIC, MO-112AC1, MQFP-52
文件頁(yè)數(shù)： 60/88頁(yè)
文件大?。?/td> 903K
代理商： ADUC842BS62-5
ADuC841/ADuC842/ADuC843
Timers/Counters
The ADuC841/ADuC842/ADuC843 have three 16-bit timer/
counters: Timer 0, Timer 1, and Timer 2. The timer/counter
hardware is included on-chip to relieve the processor core of the
overhead inherent in implementing timer/counter functionality
in software. Each timer/counter consists of two 8-bit registers:
THx and TLx (x = 0, 1, and 2). All three can be configured to
operate either as timers or as event counters.
Rev. 0 | Page 60 of 88
In timer function, the TLx register is incremented every
machine cycle. Thus, one can think of it as counting machine
cycles. Since a machine cycle on a single-cycle core consists of
one core clock period, the maximum count rate is the core clock
frequency.
In counter function, the TLx register is incremented by a 1-to-0
transition at its corresponding external input pin: T0, T1, or T2.
When the samples show a high in one cycle and a low in the
next cycle, the count is incremented. Since it takes two machine
cycles (two core clock periods) to recognize a 1-to-0 transition,
the maximum count rate is half the core clock frequency.
There are no restrictions on the duty cycle of the external input
signal, but to ensure that a given level is sampled at least once
before it changes, it must be held for a minimum of one full
machine cycle. User configuration and control of all timer
operating modes is achieved via three SFRs:
TMOD, TCON
Control and configuration for
Timers 0 and 1.
Control and configuration for
Timer 2.
Timer/Counter 0 and 1 Mode
Register
89H
00H
No
T2CON
TMOD
SFR Address
Power-On Default
Bit Addressable
Table 28. TMOD SFR Bit Designations
Bit No.
Name
7
Gate
Description
Timer 1 Gating Control.
Set by software to enable Timer/Counter 1 only while the INT1 pin is high and the TR1 control bit is set.
Cleared by software to enable Timer 1 whenever the TR1 control bit is set.
Timer 1 Timer or Counter Select Bit.
Set by software to select counter operation (input from T1 pin).
Cleared by software to select timer operation (input from internal system clock).
Timer 1 Mode Select Bit 1 (Used with M0 Bit).
Timer 1 Mode Select Bit 0.
M1
M0
0
0
TH1 operates as an 8-bit timer/counter. TL1 serves as 5-bit prescaler.
0
1
16-Bit Timer/Counter. TH1 and TL1 are cascaded; there is no prescaler.
1
0
8-Bit Autoreload Timer/Counter. TH1 holds a value that is to be reloaded into TL1 each time it
overflows.
1
1
Timer/Counter 1 Stopped.
Timer 0 Gating Control.
Set by software to enable Timer/Counter 0 only while the INT0 pin is high and the TR0 control bit is set.
Cleared by software to enable Timer 0 whenever the TR0 control bit is set.
Timer 0 Timer or Counter Select Bit.
Set by software to select counter operation (input from T0 pin).
Cleared by software to select timer operation (input from internal system clock).
Timer 0 Mode Select Bit 1.
Timer 0 Mode Select Bit 0.
M1
M0
0
0
TH0 operates as an 8-bit timer/counter. TL0 serves as a 5-bit prescaler.
0
1
16-Bit Timer/Counter. TH0 and TL0 are cascaded; there is no prescaler.
1
0
8-Bit Autoreload Timer/Counter. TH0 holds a value that is to be reloaded into TL0 each time it
overflows.
1
1
TL0 is an 8-bit timer/counter controlled by the standard Timer 0 control bits.
TH0 is an 8-bit timer only, controlled by Timer 1 control bits.
6
C/T
5
4
M1
M0
3
Gate
2
C/T
1
0
M1
M0
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