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參數(shù)資料
| 型號： | ADUC842BS62-5 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MicroConverter 12-Bit ADCs and DACs with Embedded High Speed 62-kB Flash MCU |
| 中文描述： | 8-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP52 |
| 封裝： | PLASTIC, MO-112AC1, MQFP-52 |
| 文件頁數(shù)： | 58/88頁 |
| 文件大?。?/td> | 903K |
| 代理商： | ADUC842BS62-5 |
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ADuC841/ADuC842/ADuC843
In general-purpose I/O port mode, Port 2 pins that have 1s
written to them are pulled high by the internal pull-ups
(Figure 60) and, in that state, can be used as inputs. As inputs,
Port 2 pins being pulled externally low source current because
of the internal pull-up resistors. Port 2 pins with 0s written to
them drive a logic low output voltage (V
OL
) and are capable of
sinking 1.6 mA.
Rev. 0 | Page 58 of 88
P2.6 and P2.7 can also be used as PWM outputs. When they are
selected as the PWM outputs via the CFG841/CFG842 SFR, the
PWM outputs overwrite anything written to P2.6 or P2.7.
CONTROL
READ
LATCH
INTERNAL
BUS
WRITE
TO LATCH
READ
PIN
D
CL
LATCH
Q
DV
DD
ADDR
P2.x
PIN
DV
DD
INTERNAL
PULL-UP*
*SEE FOLLOWING FIGURE FOR
DETAILS OF INTERNAL PULL-UP
Q
0
Figure 59. Port 2 Bit Latch and I/O Buffer
FROM
PORT
LATCH
2 CLK
DELAY
Q1
DV
DD
Q2
DV
DD
Q3
DV
DD
Px.x
PIN
Q4
Q
0
Figure 60. Internal Pull-Up Configuration
Port 3
Port 3 is a bidirectional port with internal pull-ups directly
controlled via the P3 SFR. Port 3 pins that have 1s written to
them are pulled high by the internal pull-ups and, in that state,
can be used as inputs. As inputs, Port 3 pins being pulled
externally low source current because of the internal pull-ups.
Port 3 pins with 0s written to them will drive a logic low output
voltage (V
OL
) and are capable of sinking 4 mA. Port 3 pins also
have various secondary functions as described in Table 26. The
alternate functions of Port 3 pins can be activated only if the
corresponding bit latch in the P3 SFR contains a 1. Otherwise,
the port pin is stuck at 0.
Table 26. Port 3 Alternate Pin Functions
Pin No.
Alternate Function
P3.0
RxD (UART Input Pin) (or Serial Data I/O in Mode 0)
P3.1
TxD (UART Output Pin) (or Serial Clock Output in Mode 0)
P3.2
INT0 (External Interrupt 0)
P3.3
INT1 (External Interrupt 1)/PWM 1/MISO
P3.4
T0 (Timer/Counter 0 External Input)
PWM External Clock/PWM 0
P3.5
T1 (Timer/Counter 1 External Input)
P3.6
WR (External Data Memory Write Strobe)
P3.7
RD (External Data Memory Read Strobe)
P3.3 and P3.4 can also be used as PWM outputs. When they are
selected as the PWM outputs via the CFG841/CFG842 SFR, the
PWM outputs overwrite anything written to P3.4 or P3.3.
READ
LATCH
INTERNAL
BUS
WRITE
TO LATCH
READ
PIN
D
CL
LATCH
Q
DV
DD
P3.x
PIN
INTERNAL
PULL-UP*
*SEE PREVIOUS FIGURE
FOR DETAILS OF
INTERNAL PULL-UP
ALTERNATE
OUTPUT
FUNCTION
ALTERNATE
INPUT
FUNCTION
Q
0
Figure 61. Port 3 Bit Latch and I/O Buffer
Additional Digital I/O
In addition to the port pins, the dedicated SPI/I
2
C pins (SCLOCK
and SDATA/MOSI) also feature both input and output func-
tions. Their equivalent I/O architectures are illustrated in
Figure 62 and Figure 64, respectively, for SPI operation and in
Figure 63 and Figure 65 for I
2
C operation. Notice that in I
2
C
mode (SPE = 0), the strong pull-up FET (Q1) is disabled,
leaving only a weak pull-up (Q2) present. By contrast, in SPI
mode (SPE = 1) the strong pull-up FET (Q1) is controlled
directly by SPI hardware, giving the pin push-pull capability.
In I
2
C mode (SPE = 0), two pull-down FETs (Q3 and Q4)
operate in parallel to provide an extra 60% or 70% of current
sinking capability. In SPI mode (SPE = 1), however, only one of
the pull-down FETs (Q3) operates on each pin, resulting in sink
capabilities identical to that of Port 0 and Port 2 pins. On the
input path of SCLOCK, notice that a Schmitt trigger conditions
the signal going to the SPI hardware to prevent false triggers
(double triggers) on slow incoming edges. For incoming signals
from the SCLOCK and SDATA pins going to I
2
C hardware, a
filter conditions the signals to reject glitches of up to 50 ns in
duration.
Notice also that direct access to the SCLOCK and SDATA/
MOSI pins is afforded through the SFR interface in I
2
C master
mode. Therefore, if you are not using the SPI or I
2
C functions,
you can use these two pins to give additional high current
digital outputs.
Q3
SCHMITT
TRIGGER
Q1
Q2 (OFF)
DV
DD
Q4 (OFF)
SCLOCK
PIN
SPE = 1 (SPI ENABLE)
HARDWARE SPI
(MASTER/SLAVE)
0
Figure 62. SCLOCK Pin I/O Functional Equivalent in SPI Mode
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| ADUC842BSZ62-3 | 功能描述:IC ADC/DAC 12BIT W/MCU 52MQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MicroConverter® ADuC8xx 標準包裝:250 系列:LPC11Uxx 核心處理器:ARM? Cortex?-M0 芯體尺寸:32-位 速度:50MHz 連通性:I²C，Microwire，SPI，SSI，SSP，UART/USART，USB 外圍設(shè)備:欠壓檢測/復位，POR，WDT 輸入/輸出數(shù):40 程序存儲器容量:96KB（96K x 8） 程序存儲器類型:閃存 EEPROM 大小:4K x 8 RAM 容量:10K x 8 電壓 - 電源 (Vcc/Vdd):1.8 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:48-LQFP 包裝:托盤 其它名稱:568-9587 |
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