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參數(shù)資料
| 型號： | ADUC832BSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 82/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC/DAC 12BIT W/MCU 52MQFP |
| 產品培訓模塊： | Process Control |
| 標準包裝： | 1 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 16MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設備： | PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲器容量： | 62KB（62K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉換器： | A/D 8x12b，D/A 2x12b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 52-QFP |
| 包裝： | 托盤 |
| 產品目錄頁面： | 738 (CN2011-ZH PDF) |
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Data Sheet
ADuC832
Rev. B | Page 83 of 92
LATCH
SRAM
A8 TO A15
A0 TO A7
D0 TO D7
(DATA)
ADuC832
P2
ALE
P0
0
298
7-
0
76
RD
WR
OE
WE
Figure 88. External Data Memory Interface (64 kB Address Space)
If access to more than 64 kB of RAM is desired, a feature unique
to the ADuC832 allows addressing up to 16 MB of external
RAM simply by adding an additional latch, as illustrated in
LATCH
ADuC832
RD
P2
ALE
P0
WR
LATCH
SRAM
OE
A8 TO A15
A0 TO A7
D0 TO D7
(DATA)
WE
A16 TO A23
0
29
87
-07
7
Figure 89. External Data Memory Interface (16 MB Address Space)
In either implementation, Port 0 (P0) serves as a multiplexed
address/data bus. It emits the low byte of the data pointer (DPL)
as an address, which is latched by a pulse of ALE prior to data
being placed on the bus by the ADuC832 (write operation) or
the SRAM (read operation). Port 2 (P2) provides the data
pointer page byte (DPP) to be latched by ALE, followed by the
data pointer high byte (DPH). If no latch is connected to P2,
DPP is ignored by the SRAM, and the 8051 standard of 64 kB
external data memory access is maintained.
POWER SUPPLIES
The ADuC832 operational power supply voltage range is 2.7 V
to 5.25 V. Although the guaranteed data sheet specifications are
given only for power supplies within 2.7 V to 3.6 V or 10% of
the nominal 5 V level, the chip functions equally well at any
power supply level between 2.7 V and 5.5 V.
Note that Figure 90 and Figure 91 refer to the MQFP package.
For the LFCSP package, connect the extra DVDD, DGND, AVDD,
and AGND in the same manner.
Separate analog and digital power supply pins (AVDD and DVDD,
respectively) allow AVDD to be relatively free of noisy digital signals
often present on the system DVDD line. However, though AVDD
and DVDD can be powered from two separate supplies if desired,
they must remain within 0.3 V of one another at all times to
avoid damaging the chip (as per the Absolute Maximum Ratings
section). Therefore, it is recommended that, unless AVDD and
DVDD are connected directly together, back-to-back Schottky
diodes be connected between them as shown in Figure 90.
DVDD
ADuC832
AGND
AVDD
0.1F
10F
ANALOG SUPPLY
10F
DGND
DIGITAL SUPPLY
02
98
7-
0
78
Figure 90. External Dual-Supply Connections
As an alternative to providing two separate power supplies,
the user can keep AVDD quiet by placing a small series resistor
and/or ferrite bead between it and DVDD, and then decoupling
AVDD separately to ground. An example of this configuration is
shown in Figure 91. With this configuration, other analog circuitry
(such as op amps and voltage reference) can be powered from
the AVDD supply line as well. The user should still include back-
to-back Schottky diodes between AVDD and DVDD to protect
from power-up and power-down transient conditions that may
separate the two supply voltages momentarily.
10F
DVDD
ADuC832
AGND
DGND
0.1F
DIGITAL SUPPLY
1.6
BEAD
AVDD
0
29
87
-07
9
Figure 91. External Single-Supply Connections
Note that, in both Figure 90 and Figure 91, a large value (10 μF)
reservoir capacitor is connected to DVDD and a separate 10 μF
capacitor is connected to AVDD. Also, local small-value (0.1 μF)
capacitors are located at each AVDD pin of the chip. As per stan-
dard design practice, be sure to include all of these capacitors,
and ensure that the smaller capacitors are close to each AVDD
pin with trace lengths as short as possible. Connect the ground
terminal of each of these capacitors directly to the underlying
ground plane. Finally, it should also be noted that, at all times,
the analog and digital ground pins on the ADuC832 must be
referenced to the same system ground reference point.
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