參數(shù)資料
型號: ADUC832BSZ
廠商: Analog Devices Inc
文件頁數(shù): 49/92頁
文件大?。?/td> 0K
描述: IC ADC/DAC 12BIT W/MCU 52MQFP
產(chǎn)品培訓(xùn)模塊: Process Control
標(biāo)準(zhǔn)包裝: 1
系列: MicroConverter® ADuC8xx
核心處理器: 8052
芯體尺寸: 8-位
速度: 16MHz
連通性: EBI/EMI,I²C,SPI,UART/USART
外圍設(shè)備: PSM,溫度傳感器,WDT
輸入/輸出數(shù): 34
程序存儲器容量: 62KB(62K x 8)
程序存儲器類型: 閃存
EEPROM 大小: 4K x 8
RAM 容量: 2.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b,D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 52-QFP
包裝: 托盤
產(chǎn)品目錄頁面: 738 (CN2011-ZH PDF)
Data Sheet
ADuC832
Rev. B | Page 53 of 92
SOURCE/SINK CURRENT (mA)
4
0
5
10
15
O
UT
P
UT
V
O
L
T
AG
E
(
V
)
3
1
0
DAC LOADED WITH 0000H
DAC LOADED WITH 0FFFH
02
98
7-
0
43
Figure 54. Source and Sink Current Capability with VREF = AVDD = 3 V
To reduce the effects of the saturation of the output amplifier at
values close to ground and to give reduced offset and gain errors,
the internal buffer can be bypassed. This is done by setting the
DBUF bit in the CFG832 register. This allows a full rail-to-rail
output from the DAC, which should then be buffered externally
using a dual-supply op amp to obtain a rail-to-rail output. This
external buffer should be located as near as physically possible
to the DAC output pin on the PCB. Note that the unbuffered
mode only works in the 0 V to VREF range.
To drive significant loads with the DAC outputs, external
buffering may be required (even with the internal buffer
enabled), as illustrated in Figure 55. A list of recommended op
amps is shown in Table 20.
ADuC832
DAC0
DAC1
0
29
87
-0
44
Figure 55. Buffering the DAC Outputs
The DAC output buffer also features a high impedance disable
function. In the chip’s default power-on state, both DACs are
disabled, and their outputs are in a high impedance state (or
three-state) where they remain inactive until enabled in
software. This means that if a zero output is desired during
power-up or power-down transient conditions, then a pull-
down resistor must be added to each DAC output. Assuming
this resistor is in place, the DAC outputs remain at ground
potential whenever the DAC is disabled.
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