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| 型號(hào)： | ADUC814 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | MicroConverter, Small Package 12-Bit ADC with Embedded Flash MCU |
| 中文描述： | MicroConverter的，小包裝12位ADC，嵌入式閃存MCU |
| 文件頁(yè)數(shù)： | 49/72頁(yè) |
| 文件大?。?/td> | 846K |
| 代理商： | ADUC814 |
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ADuC814
TCON
SFR Address
Power-On Default
Bit Addressable
Rev. A | Page 49 of 72
Timer/Counter 0 and 1 Control Register
88H
00H
Yes
TF1
TR1
TF0
TR0
IE1
1
IT1
1
IE0
IT0
1
1
These bits are not used in the control of Timer/Counter 0 and 1, but are used instead in the control and monitoring of the external INT0 and INT1 interrupt pins.
Table 23. TCON SFR Bit Designations
Bit No.
Name
Description
7
TF1
Timer 1 Overflow Flag.
Set by hardware on a Timer/Counter 1 overflow.
Cleared by hardware when the program counter (PC) vectors to the interrupt service routine.
6
TR1
Timer 1 Run Control Bit.
Set by the user to turn on Timer/Counter 1.
Cleared by the user to turn off Timer/Counter 1.
5
TF0
Timer 0 Overflow Flag.
Set by hardware on a Timer/Counter 0 overflow.
Cleared by hardware when the PC vectors to the interrupt service routine.
4
TR0
Timer 0 Run Control Bit.
Set by the user to turn on Timer/Counter 0.
Cleared by the user to turn off Timer/Counter 0.
3
IE1
External Interrupt 1 (INT1) Flag.
Set by hardware by a falling edge or zero level being applied to external interrupt pin INT1, depending on bit IT1
state.
Cleared by hardware when the when the PC vectors to the interrupt service routine only if the interrupt was
transition-activated. If level-activated, the external requesting source controls the request flag, rather than the on-
chip hardware.
2
IT1
External Interrupt 1 (IE1) Trigger Type.
Set by software to specify edge-sensitive detection, that is, 1-to-0 transition.
Cleared by software to specify level-sensitive detection, that is, zero level.
1
IE0
External Interrupt 0 (INT0) Flag.
Set by hardware by a falling edge or zero level being applied to external interrupt pin INT0, depending on bit IT0
state.
Cleared by hardware when the PC vectors to the interrupt service routine, but only if the interrupt was transition-
activated. If level-activated, the external requesting source controls the request flag, rather than the on-chip
hardware.
0
IT0
External Interrupt 0 (IE0) Trigger Type.
Set by software to specify edge-sensitive detection, that is, 1-to-0 transition.
Cleared by software to specify level-sensitive detection, that is, zero level.
Timer/Counter 0 and 1 Data Registers
Each timer consists of two 8-bit registers. These can be used as independent registers or combined to be a single 16-bit register, depending
on the timer mode configuration.
TH0 and TL0
SFR Address
Timer 0 high byte and low byte.
8CH, 8AH, respectively
TH1 and TL1
SFR Address
Timer 1 high byte and low byte.
8DH, 8BH, respectively
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