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| 型號： | ADUC812BSZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/57頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU FLASH 12BIT ADC 52MQFP |
| 標準包裝： | 800 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 16MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設備： | PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲器容量： | 8KB（8K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 640 x 8 |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉換器： | A/D 8x12b，D/A 2x12b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 52-QFP |
| 包裝： | 帶卷 (TR) |
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REV.
ADuC812
–28–
I2CADD
I
2C Address Register
Function
Holds the I
2C peripheral address for
the part. It may be overwritten by
the user code. Application note uC001
at www.analog.com/microconverter
describes the format of the I
2C
standard 7-bit address in detail.
SFR Address
9BH
Power-On Default Value 55H
Bit Addressable
No
I2CDAT
I
2C Data Register
Function
The I2CDAT SFR is written by the
user to transmit data over the I
2C
interface or read by user code to read
data just received by the I
2C interface.
User software should only access
I2CDAT once per interrupt cycle.
SFR Address
9AH
Power-On Default Value 00H
Bit Addressable
No
O
D
ME
D
MO
C
MI
D
MM
C
2
IS
R
C
2
IX
T
C
2
II
C
2
I
Table XII. I2CCON SFR Bit Designations
Bit
Name
Description
7
MDO
I
2C Software Master Data Output Bit (Master Mode Only).
This data bit is used to implement a master I
2C transmitter interface in software. Data written to
this bit will be output on the SDATA pin if the data output enable (MDE) bit is set.
6
MDE
I
2C Software Master Data Output Enable Bit (Master Mode Only).
Set by the user to enable the SDATA pin as an output (Tx). Cleared by the user to enable SDATA
pin as an input (Rx).
5
MCO
I
2C Software Master Data Output Bit (Master Mode Only).
This data bit is used to implement a master I
2C transmitter interface in software. Data written to
this bit will be output on the SCLOCK pin.
4
MDI
I
2C Software Master Data Input Bit (Master Mode Only).
This data bit is used to implement a master I
2C receiver interface in software. Data on the
SDATA pin is latched into this bit on SCLOCK if the Data Output Enable (MDE) = 0.
3
I2CM
I
2C Master/Slave Mode Bit.
Set by user to enable I
2C software master mode. Cleared by user to enable I2C hardware slave mode.
2
I2CRS
I
2C Reset Bit (Slave Mode Only).
Set by user to reset the I
2C interface. Cleared by user for normal I2C operation.
1
I2CTX
I
2C Direction Transfer Bit (Slave Mode Only).
Set by the MicroConverter if the interface is transmitting. Cleared by the MicroConverter if the
interface is receiving.
0
I2CI
I
2C Interrupt Bit (Slave Mode Only).
Set by the MicroConverter after a byte has been transmitted or received. Cleared by user software.
I
2C* COMPATIBLE INTERFACE
The ADuC812 supports a 2-wire serial interface mode that is
I
2C compatible. The I2C compatible interface shares its pins with
the on-chip SPI interface and therefore the user can only enable
one or the other interface at any given time (see SPE in Table IX).
An application note describing the operation of this interface as
implemented is available from the MicroConverter website at
www.analog.com/microconverter. This interface can be configured
as a software master or hardware slave, and uses two pins in the
interface.
SDATA
Serial Data I/O Pin
SCLOCK
Serial Clock
Three SFRs are used to control the I
2C compatible interface.
These are described below:
I2CCON
I
2C Control Register
SFR Address
E8H
Power-On Default Value
00H
Bit Addressable
Yes
*Purchase of licensed I
2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips
I
2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
F
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