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參數(shù)資料
型號(hào)： ADUC7121BBCZ-RL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 59/96頁(yè)
文件大?。?/td> 0K
描述： PRECISION ANALOG MCU I.C
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 41.78MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 126KB（63K x 16）
程序存儲(chǔ)器類(lèi)型： 閃存
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 9x12b，D/A 4x12b
振蕩器型： 內(nèi)部
工作溫度： -10°C ~ 95°C
封裝/外殼： 108-LFBGA，CSPBGA
包裝： 標(biāo)準(zhǔn)包裝
其它名稱(chēng)： ADUC7121BBCZ-RLDKR
ADuC7121
Data Sheet
Rev. B | Page 62 of 96
I2C PERIPHERALS
The ADuC7121 incorporates two I2C peripherals that may be
configured as a fully I2C-compatible bus master device or as a
fully I2C-compatible bus slave device. Both peripherals are
identical.
The two pins used for data transfer, SDA and SCL, are configured
in a wired-AND format that allows arbitration in a multimaster
system. These pins require external pull-up resistors. Typical
pull-up values are between 4.7 kΩ and 10 kΩ.
The address of the I2C bus peripheral in the I2C bus system is
programmed by the user. This ID can be modified any time a
transfer is not in progress. The user can configure the interface
to respond to four slave addresses.
The transfer sequence of an I2C system consists of a master device
initiating a transfer by generating a start condition while the bus
is idle. The master transmits the slave device address and the
direction of the data transfer (R/W) during the initial address
transfer. If the master does not lose arbitration and the slave
acknowledges, the data transfer is initiated. This continues until
the master issues a stop condition and the bus becomes idle.
The I2C peripheral can only be configured as a master or slave
at any given time. The same I2C channel cannot simultaneously
support master and slave modes. The I2C interface on the
ADuC7121 includes the following features:
Support for repeated start conditions. In master mode, the
ADuC7121 can be programmed to generate a repeated
start. In slave mode, the ADuC7121 recognizes repeated
start conditions.
In master and slave modes, the device recognizes both
7-bit and 10-bit bus addresses.
In I2C Master mode, the ADuC7121 supports continuous
reads from a single slave up to 512 bytes in a single transfer
sequence.
Clock stretching is supported in both master and slave
modes.
In slave mode, the ADuC7121 can be programmed to
return a no acknowledge. This allows the validation of
checksum bytes at the end of I2C transfers.
Bus arbitration in master mode is supported.
Internal and external loopback modes are supported for
I2C hardware testing in loopback mode.
The transmit and receive circuits in both master and slave
mode contain 2-byte FIFOs. Status bits are available to the
user to control these FIFOs.
Configuring External Pins for I2C Functionality
The I2C pins of the ADuC7121 device are P0.0 and P0.1 for
I2C0, and P1.0 and P1.1 for I2C1. P0.0 and P1.0 are the I2C clock
signals, and P0.1 and P1.1 are the I2C data signals. For instance,
to configure the I2C0 pins (SCL0, SDA0), Bit 0 and Bit 4 of the
GP0CON register must be set to 1 to enable I2C mode. To
configure the I2C1 pins (SCL1, SDA1), Bit 1 and Bit 5 of the
GP1CON register must be set to 1 to enable I2C mode, as shown
SERIAL CLOCK GENERATION
The I2C master in the system generates the serial clock for a
transfer. The master channel can be configured to operate in
fast mode (400 kHz) or standard mode (100 kHz). The bit rate
is defined in the I2CDIV MMR as follows:
)
(2
)
2
(
DIVL
DIVH
UCLK
CLOCK
SERIAL
f
where:
fUCLK
= clock before the clock divider.
DIVH
= the high period of the clock.
DIVL
= the low period of the clock.
Thus, for 100 kHz operation
DIVH
= DIVL = 0xCF
and for 400 kHz
DIVH
= 0x28, DIVL = 0x3C
The I2CDIV register corresponds to DIVH:DIVL.
I2C BUS ADDRESSES
Slave Mode
In slave mode, the registers I2CxID0, I2CxID1, I2CxID2, and
I2CxID3 contain the device IDs. The device compares the four
I2CxIDx registers to the address byte received from the bus
master. To be correctly addressed, the 7 MSBs of either ID
register must be identical to that of the 7 MSBs of the first
received address byte. The LSB of the ID registers (the transfer
direction bit) is ignored in the process of address recognition.
The ADuC7121 also supports 10-bit addressing mode. When
Bit 1 of I2CxSCON (ADR10EN bit) is set to 1, then one 10-bit
address is supported in slave mode and is stored in registers
I2CxID0 and I2CxID1. The 10-bit address is derived as follows:
I2CxID0[0] is the read/write bit and is not part of the I2C address.
I2CxID0[7:1] = Address Bits[6:0].
I2CxID1[2:0] = Address Bits[9:7].
I2CxID1[7:3] must be set to 11110b.
Master Mode
In master mode, the I2CxADR0 register is programmed with
the I2C address of the device.
In 7-bit address mode, I2CxADR0[7:1] are set to the device
address. I2CxADR0[0] is the read/write bit.
In 10-bit address mode, the 10-bit address is created as follows:
I2CxADR0[7:3] must be set to 11110b.
I2CxADR0[2:1] = Address Bits[9:8].
I2CxADR1[7:0] = Address Bits[7:0].
I2CxADR0[0] is the read/write bit.
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