- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1900 > ADUC7121BBCZ-RL (Analog Devices Inc)PRECISION ANALOG MCU I.C PDF資料下載
參數(shù)資料
| 型號： | ADUC7121BBCZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 33/96頁 |
| 文件大?。?/td> | 0K |
| 描述： | PRECISION ANALOG MCU I.C |
| 標準包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 41.78MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器容量： | 126KB（63K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 8K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 數(shù)據(jù)轉換器： | A/D 9x12b，D/A 4x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -10°C ~ 95°C |
| 封裝/外殼： | 108-LFBGA，CSPBGA |
| 包裝： | 標準包裝 |
| 其它名稱： | ADUC7121BBCZ-RLDKR |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁當前第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁
Data Sheet
ADuC7121
Rev. B | Page 39 of 96
EXECUTION TIME FROM SRAM AND FLASH/EE
This section describes SRAM and Flash/EE access times during
execution for applications where execution time is critical.
Execution from SRAM
Fetching instructions from SRAM takes one clock cycle because
the access time of the SRAM is 2 ns and a clock cycle is 22 ns
minimum. However, if the instruction involves reading or
writing data to memory, one extra cycle must be added if the
data is in SRAM (or three cycles if the data is in Flash/EE), one
cycle to execute the instruction, and two cycles to retrieve the
32-bit data from Flash/EE. A control flow instruction, such as a
branch instruction, takes one cycle to fetch, but it also takes two
cycles to fill the pipeline with the new instructions.
Execution from Flash/EE
Because the Flash/EE width is 16 bits and access time for 16-bit
words is 23 ns, execution from Flash/EE cannot be accomplished
in one cycle (as can be done from SRAM when the CD bit = 0). In
addition, some dead times are needed before accessing data for
any value of CD bits.
In ARM mode, where instructions are 32 bits, two cycles are
needed to fetch any instruction when CD = 0. In Thumb mode,
where instructions are 16 bits, one cycle is needed to fetch any
instruction.
Timing is identical in both modes when executing instructions
that involve using the Flash/EE for data memory. If the instruction
to be executed is a control flow instruction, an extra cycle is
needed to decode the new address of the program counter and
then four cycles are needed to fill the pipeline. A data processing
instruction involving only core registers does not require any
extra clock cycles, but if it involves data in Flash/EE, one
additional clock cycle is needed to decode the address of the
data and two additional cycles are needed to obtain the 32-bit
data from Flash/EE. An extra cycle must also be added before
fetching another instruction. Data transfer instructions are
more complex and are summarized in Table 46.
Table 46. Execution Cycles in ARM/Thumb Mode
Instructions
Fetch
Cycles
Dead
Time
Data Access
Dead
Time
LD
2/1
1
2
1
LDH
2/1
1
LDM/PUSH
2/1
N
2 × N
N
STR
2/1
1
2 × 20 s
1
STRH
2/1
1
20 s
1
STRM/POP
2/1
N
2 × N × 20 s
N
With 1 < N ≤ 16, N is the number of bytes of data to load or
store in the multiple load/store instruction. The SWAP instruction
combines an LD and STR instruction with only one fetch,
giving a total of eight cycles plus 40 μs.
RESET AND REMAP
The ARM exception vectors are situated at the bottom of the
memory array, from Address 0x00000000 to Address 0x00000020,
as shown in Figure 27.
Figure 27. Remap for Exception Execution
By default and after any reset, the Flash/EE is mirrored at the
bottom of the memory array. The remap function allows the
programmer to mirror the SRAM at the bottom of the memory
array, facilitating execution of exception routines from SRAM
instead of from Flash/EE. This means exceptions are executed
twice as fast, with the exception being executed in ARM mode
(32 bits), and the SRAM being 32 bits wide instead of being
16-bit wide Flash/EE memory.
Remap Operation
When a reset occurs on the ADuC7121, execution starts auto-
matically in factory programmed internal configuration code.
This kernel is hidden and cannot be accessed by user code.
If the ADuC7121 is in normal mode (the P3.7/BM/PLAO[11] pin
is high), it executes the power-on configuration routine of the
kernel and then jumps to the Reset Vector Address 0x00000000 to
execute the user’s reset exception routine. Because the Flash/EE is
mirrored at the bottom of the memory array at reset, the reset
interrupt routine must always be written in Flash/EE.
The remap is performed from Flash/EE by setting Bit 0 of the
remap register. Precautions must be taken to execute this
command from Flash/EE (above Address 0x00080020) and not
from the bottom of the array because this, the defined memory
space, is replaced by the SRAM.
This operation is reversible: the Flash/EE can be remapped at
Address 0x00000000 by clearing Bit 0 of the remap MMR.
Precaution must again be taken to execute the remap function
from outside the mirrored area. Any kind of reset remaps the
Flash/EE memory at the bottom of the array.
KERNEL
INTERRUPT
SERVICE ROUTINES
INTERRUPT
SERVICE ROUTINES
ARM EXCEPTION
VECTOR ADDRESSES
0x00000020
0x00041FFF
0x0008FFFF
0xFFFFFFFF
FLASH/EE
SRAM
MIRROR SPACE
0x00000000
0x00040000
0x00080000
09492-
026
相關PDF資料 |
PDF描述 |
|---|---|
| ADUC7122BBCZ-RL | PRECISION ANALOG MCU I.C |
| ADUC7126BSTZ126-RL | IC MCU 16/32B 126KB FLASH 80LQFP |
| ADUC7129BSTZ126 | IC DAS MCU ARM7 ADC/DDS 80-LQFP |
| ADUC812BSZ-REEL | IC MCU FLASH 12BIT ADC 52MQFP |
| ADUC814BRU | IC ADC 12BIT W/FLASH MCU 28TSSOP |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADUC7122 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI? MCU |
| ADUC7122BBCZ | 功能描述:IC ARM7TDMI MCU 126KB 108CSPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MicroConverter® ADuC7xxx 標準包裝:250 系列:56F8xxx 核心處理器:56800E 芯體尺寸:16-位 速度:60MHz 連通性:CAN，SCI，SPI 外圍設備:POR，PWM，溫度傳感器，WDT 輸入/輸出數(shù):21 程序存儲器容量:40KB（20K x 16） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:6K x 16 電壓 - 電源 (Vcc/Vdd):2.25 V ~ 3.6 V 數(shù)據(jù)轉換器:A/D 6x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 125°C 封裝/外殼:48-LQFP 包裝:托盤 配用:MC56F8323EVME-ND - BOARD EVALUATION MC56F8323 |
| ADUC7122BBCZ-RL | 功能描述:PRECISION ANALOG MCU I.C RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MicroConverter® ADuC7xxx 標準包裝:38 系列:Encore!® XP® 核心處理器:eZ8 芯體尺寸:8-位 速度:5MHz 連通性:IrDA，UART/USART 外圍設備:欠壓檢測/復位，LED，POR，PWM，WDT 輸入/輸出數(shù):16 程序存儲器容量:4KB（4K x 8） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:1K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 3.6 V 數(shù)據(jù)轉換器:- 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 105°C 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 包裝:管件 其它名稱:269-4116Z8F0413SH005EG-ND |
| ADUC7124 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Precision Analog Microcontroller, 12-Bit Analog I/O, Large Memory, ARM7TDMI MCU with Enhanced IRQ Handler |
| ADUC7124BCPZ126 | 功能描述:IC DAS MCU ARM7 ADC/DDS 64LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MicroConverter® ADuC7xxx 標準包裝:250 系列:LPC11Uxx 核心處理器:ARM? Cortex?-M0 芯體尺寸:32-位 速度:50MHz 連通性:I²C，Microwire，SPI，SSI，SSP，UART/USART，USB 外圍設備:欠壓檢測/復位，POR，WDT 輸入/輸出數(shù):40 程序存儲器容量:96KB（96K x 8） 程序存儲器類型:閃存 EEPROM 大小:4K x 8 RAM 容量:10K x 8 電壓 - 電源 (Vcc/Vdd):1.8 V ~ 3.6 V 數(shù)據(jù)轉換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:48-LQFP 包裝:托盤 其它名稱:568-9587 |
發(fā)布緊急采購，3分鐘左右您將得到回復。