參數(shù)資料
型號： ADUC7020
廠商： Analog Devices, Inc.
英文描述： Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
中文描述： 精密模擬微控制器的12位模擬I / O，ARM7TDMI的微控制器
文件頁數(shù)： 12/80頁
文件大?。?/td> 840K
代理商： ADUC7020
ADuC702x Series
Preliminary Technical Data
PIN FUNCTION DESCRIPTIONS – ADUC7024/ADUC7025
Table 4. Pin Function Descriptions
Rev. PrB | Page 12 of 80
Pin#
Mnemonic
Type
*
Function
1
2
3
4
5
6
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
I
I
I
I
I
I
Single-ended or differential Analog input 4
Single-ended or differential Analog input 5
Single-ended or differential Analog input 6
Single-ended or differential Analog input 7
Single-ended or differential Analog input 8
Single-ended or differential Analog input 9
Ground voltage reference for the ADC. For optimal performance the analog
power supply should be separated from IOGND and DGND
Bias point or Negative Analog Input of the ADC in pseudo differential mode.
Must be connected to the ground of the signal to convert. This bias point
must be between 0V and 1V
DAC0 Voltage Output / Single-ended or differential Analog input 12
DAC1 Voltage Output / Single-ended or differential Analog input 13
JTAG Test Port Input - Test Mode Select. Debug and download access
JTAG Test Port Input – Test Data In. Debug and download access
General Purpose Input-Output Port 4.6/ Programmable Logic Array Output
Element 14
General Purpose Input-Output Port 4.7/ Programmable Logic Array Output
Element 15
Multifunction I/O pin:
Boot Mode. The ADuC7024/ADuC7025 will enter download mode if BM is low
at reset and will execute code if BM is pulled high at reset through a 1kOhm
resistor/ General Purpose Input-Output Port 0.0 / Voltage Comparator
Output/ Programmable Logic Array Input Element 7
Multifunction pin: driven low after reset
General Purpose Output Port 0.6 / Timer 1 Input / Power on reset output /
Programmable Logic Array Output Element 3
JTAG Test Port Input - Test Clock. Debug and download access
JTAG Test Port Output - Test Data Out. Debug and download access
Ground for GPIO. Typically connected to DGND
3.3V Supply for GPIO and input of the on-chip voltage regulator.
2.5V. Output of the on-chip voltage regulator. Must be connected to a 0.47
μ
F
capacitor to DGND
Ground for core logic.
General Purpose Input-Output Port 3.0/ PWM phase 0 high side output /
Programmable Logic Array Input Element 8
General Purpose Input-Output Port 3.1/ PWM phase 0 low side output /
Programmable Logic Array Input Element 9
General Purpose Input-Output Port 3.2/ PWM phase 1 high side output /
Programmable Logic Array Input Element 10
General Purpose Input-Output Port 3.3/ PWM phase 1 low side output /
Programmable Logic Array Input Element 11
General Purpose Input-Output Port 0.3 / JTAG Test Port Input – Test Reset.
Debug and download access / ADC
BUSY
signal output
Reset Input. (active low)
General Purpose Input-Output Port 3.4 / PWM phase 2 high side output /
Programmable Logic Array Input 12
General Purpose Input-Output Port 3.5 / PWM phase 2 low side output /
Programmable Logic Array Input Element 13
7
GND
REF
S
8
ADCNEG
I
9
10
11
12
DAC0**/ADC12
DAC1**/ADC13
TMS
TDI
I/O
I/O
I
I
13
P4.6/PLAO[14]
I/O
14
P4.7/PLAO[15]
I/O
15
BM/P0.0/CMP
OUT
/PLAI[7]
I/O
16
P0.6/T1/MRST/PLAO[3]
O
17
18
19
20
TCK
TDO
IOGND
IOV
DD
I
O
S
S
21
LV
DD
S
22
DGND
S
23
P3.0/PWM0
H
/PLAI[8]
I/O
24
P3.1/PWM0
L
/PLAI[9]
I/O
25
P3.2/PWM1
H
/PLAI[10]
I/O
26
P3.3/PWM1
L
/PLAI[11]
I/O
27
P0.3/TRST/ADC
BUSY
I/O
28
RST
I
29
P3.4/PWM2
H
/PLAI[12]
I/O
30
P3.5/PWM2
L
/PLAI[13]
I/O
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