參數(shù)資料
型號(hào): ADSP-TS101SAB2Z100
廠商: Analog Devices Inc
文件頁(yè)數(shù): 16/48頁(yè)
文件大?。?/td> 0K
描述: IC DSP CTRLR 6MBIT 300MHZ 484BGA
標(biāo)準(zhǔn)包裝: 1
系列: TigerSHARC®
類型: 定點(diǎn)/浮點(diǎn)
接口: 主機(jī)接口,連接端口,多處理器
時(shí)鐘速率: 300MHz
非易失內(nèi)存: 外部
芯片上RAM: 768kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.20V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 484-BFBGA
供應(yīng)商設(shè)備封裝: 484-PBGA(19x19)
包裝: 托盤(pán)
ADSP-TS101S
Rev. C
|
Page 23 of 48
|
May 2009
Table 22. Reference Clocks—System Clock (SCLK) Cycle Time
Parameter
Description
Min
Max
Unit
tSCLK
1, 2, 3, 4
System Clock Cycle Time
10
25
ns
tSCLKH
System Clock Cycle High Time
0.4 × tSCLK
0.6 × tSCLK
ns
tSCLKL
System Clock Cycle Low Time
0.4 × tSCLK
0.6 × tSCLK
ns
tSCLKJ
5, 6
System Clock Jitter Tolerance
500
ps
1 For more information, see Table 3 on Page 12.
3 LCLK_P and SCLK_P must be connected to the same source.
4 The value of (tSCLK / LCLKRAT2-0) must not violate the specification for tCCLK.
5 Actual input jitter should be combined with ac specifications for accurate timing analysis.
6 Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.
Figure 11. Reference Clocks—System Clock (SCLK) Cycle Time
Table 23. Reference Clocks—Test Clock (TCK) Cycle Time
Parameter
Description
Min
Max
Unit
tTCK
Test Clock (JTAG) Cycle Time
Greater of 30 or tCCLK × 4
ns
tTCKH
Test Clock (JTAG) Cycle High Time
12.5
ns
tTCKL
Test Clock (JTAG) Cycle Low Time
12.5
ns
Figure 12. Reference Clocks—Test Clock (TCK) Cycle Time
Table 24. Power-Up Timing1
Parameter
Min
Max
Unit
Timing Requirement
tVDD_IO
VDD_IO Stable and Within Specification After VDD and VDD_A
Are Stable and Within Specification
>0
ms
1 For information about power supply sequencing and monitoring solutions, please visit http://www.analog.com/sequencing.
Figure 13. Power-Up Sequencing Timing
SCLK_P
tSCLK
tSCLKH
tSCLKL
tSCLKJ
SCLK_P
tSCLK
tSCLKH
tSCLKL
tSCLKJ
TCK
tTCK
tTCKH
tTCKL
VDD
VDD_A
VDD_IO
tVDD_IO
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