參數(shù)資料
型號(hào)： ADSP-BF535PKB-300
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 6/44頁(yè)
文件大?。?/td> 0K
描述： IC DSP CONTROLLER 16BIT 260 BGA
產(chǎn)品培訓(xùn)模塊： Blackfin® Processor Core Architecture Overview
Blackfin® Device Drivers
Blackfin® Optimizations for Performance and Power Consumption
Blackfin® System Services
標(biāo)準(zhǔn)包裝： 1
系列： Blackfin®
類(lèi)型： 定點(diǎn)
接口： PCI，SPI，SSP，UART，USB
時(shí)鐘速率： 300MHz
非易失內(nèi)存： 外部
芯片上RAM： 308kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.50V
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 260-BBGA
供應(yīng)商設(shè)備封裝： 260-PBGA（19x19）
包裝： 托盤(pán)
ADSP-BF535
–14–
REV. A
SSEL fields define a divide ratio between the core clock (CCLK)
and the system clock. Table 5 illustrates the system clock ratios.
The system clock is supplied to the CLKOUT_SCLK0 pin.
The maximum frequency of the system clock is fSCLK. Note that
the divisor ratio must be chosen to limit the system clock
frequency to its maximum of fSCLK. The reset value of the
SSEL1–0 is determined by sampling the SSEL1 and SSEL0 pins
during reset. The SSEL value can be changed dynamically by
writing the appropriate values to the PLL control register
(PLL_CTL), as described in the ADSP-BF535 Blackfin Processor
Hardware Reference.
Booting Modes
The ADSP-BF535 has three mechanisms (listed in Table 6) for
automatically loading internal L2 memory after a reset. A fourth
mode is provided to execute from external memory, bypassing
the boot sequence.
The BMODE pins of the reset configuration register, sampled
during power-on resets and software initiated resets, implement
these modes:
Execute from 16-bit external memory—Execution
starts from address 0x2000000 with 16-bit packing.
The boot ROM is bypassed in this mode.
Boot from 8-bit external flash memory—The 8-bit flash
boot routine located in boot ROM memory space is set
up using asynchronous Memory Bank 0. All configura-
tion settings are set for the slowest device possible
(3-cycle hold time; 15-cycle R/W access times; 4-cycle
setup).
Boot from SPI serial EEPROM (8-bit addressable)—
The SPI0 uses PF10 output pin to select a single SPI
EPROM device, submits a read command at address
0x00, and begins clocking data into the beginning of L2
memory. An 8-bit addressable SPI compatible EPROM
must be used.
Boot from SPI serial EEPROM (16-bit addressable)—
The SPI0 uses PF10 output pin to select a single SPI
EPROM device, submits a read command at address
0x0000, and begins clocking data into the beginning of
L2 memory. A 16-bit addressable SPI compatible
EPROM must be used.
For each of the boot modes described above, a four-byte value is
first read from the memory device. This value is used to specify
a subsequent number of bytes to be read into the beginning of
L2 memory space. Once each of the loads is complete, the
processor jumps to the beginning of L2 space and begins
execution.
In addition, the reset configuration register can be set by appli-
cation code to bypass the normal boot sequence during a software
reset. For this case, the processor jumps directly to the beginning
of L2 memory space.
To augment the boot modes, a secondary software loader is
provided that adds additional booting mechanisms. This
secondary loader provides the capability to boot from PCI, 16-bit
flash memory, fast flash, variable baud rate, and so on.
Instruction Set Description
The Blackfin processor family assembly language instruction set
employs an algebraic syntax designed for ease of coding and read-
ability. The instructions have been specifically tuned to provide
a flexible, densely encoded instruction set that compiles to a very
small final memory size. The instruction set also provides fully
featured multifunction instructions that allow the programmer
to use many of the processor core resources in a single instruction.
Coupled with many features more often seen on microcontrol-
lers, this instruction set is very efficient when compiling C and
C++ source code. In addition, the architecture supports both a
user (algorithm/application code) and a supervisor (O/S kernel,
device drivers, debuggers, ISRs) mode of operations, allowing
multiple levels of access to core processor resources.
The assembly language, which takes advantage of the processor’s
unique architecture, offers the following advantages:
Seamlessly integrated DSP/CPU features are optimized
for both 8-bit and 16-bit operations.
A super pipelined multi issue load/store modified Harvard
architecture, which supports two 16-bit MAC or four 8-
bit ALU + two load/store + two pointer updates per cycle.
All registers, I/O, and memory are mapped into a unified
4 Gbyte memory space providing a simplified program-
ming model.
Table 5. System Clock Ratios
Signal
Name
Divider
Ratio
Example Frequency
Ratios (MHz)
SSEL1– 0 CCLK/SCLK
CCLK
SCLK
00
2:1
266
133
01
2.5:1
275
110
10
3:1
300
100
11
4:1
300
75
Table 6. Booting Modes
BMODE2–0
Description
000
Execute from 16-bit external memory
(Bypass Boot ROM)
001
Boot from 8-bit flash
010
Boot from SPI0 serial ROM
(8-bit address range)
011
Boot from SPI0 serial ROM
(16-bit address range)
100 – 111
Reserved
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