參數(shù)資料
型號(hào)： ADSP-BF531SBST400
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： Circular Connector Series:97
中文描述： 16-BIT, 40 MHz, OTHER DSP, PQFP176
封裝： 24 X 24 MM, LQFP-176
文件頁數(shù)： 42/56頁
文件大小： 671K
代理商： ADSP-BF531SBST400
Rev. 0
|
Page 42 of 56
|
March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
TEST CONDITIONS
All timing parameters appearing in this data sheet were mea-
sured under the conditions described in this section.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to the point when they
start driving. The output enable time t
ENA
is the interval from
the point when a reference signal reaches a high or low voltage
level to the point when the output starts driving as shown in the
Output Enable/Disable diagram (
Figure 33
). The time
t
ENA_MEASURED
is the interval from when the reference signal
switches to when the output voltage reaches 2.0 V (output high)
or 1.0 V (output low). Time t
TRIP
is the interval from when the
output starts driving to when the output reaches the 1.0 V or
2.0 V trip voltage. Time t
ENA
is calculated as shown in the
equation:
If multiple pins (such as the data bus) are enabled, the measure-
ment value is that of the first pin to start driving.
Output Disable Time
Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by
V is dependent on the capacitive load, C
L
and the
load current, I
L
. This decay time can be approximated by the
equation:
The output disable time t
DIS
is the difference between
t
DIS_MEASURED
and t
DECAY
as shown in
Figure 33
. The time
t
DIS_MEASURED
is the interval from when the reference signal
switches to when the output voltage decays
V from the mea-
sured output high or output low voltage. The time t
DECAY
is
calculated with test loads C
L
and I
L
, and with
V equal to 0.5 V.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate t
DECAY
using the equation given above. Choose
V to be the difference between the ADSP-BF531/2/3 proces-
sor’s output voltage and the input threshold for the device
requiring the hold time. A typical
V will be 0.4 V. C
L
is the
total bus capacitance (per data line), and I
L
is the total leakage or
three-state current (per data line). The hold time will be t
DECAY
plus the minimum disable time (for example, t
DSDAT
for an
SDRAM write cycle).
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see
Figure 34
).
Figure 36
through
Figure 43 on
Page 44
show how output rise time varies with capacitance. The
delay and hold specifications given should be derated by a factor
derived from these figures. The graphs in these figures may not
be linear outside the ranges shown.
t
ENA
t
ENA_MEASURED
t
TRIP
–
=
t
DECAY
C
L
V
(
)
I
L
=
Figure 33. Output Enable/Disable
Figure 34. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
Figure 35. Voltage Reference Levels for AC
Measurements (Except Output Enable/Disable)
REFERENCE
SIGNAL
t
DIS
OUTPUT STARTS DRIVING
V
OH
(MEASURED)
V
V
OL
(MEASURED) +
V
t
DIS_MEASURED
V
OH
(MEASURED)
V
OL
(MEASURED)
2.0V
1.0V
V
OH
(MEASURED)
V
OL
(MEASURED)
t
TRIP
HIGH IMPEDANCE STATE.
TEST CONDITIONS CAUSE THIS
VOLTAGE TO BE APPROXIMATELY 1.5V.
OUTPUT STOPS DRIVING
t
ENA
t
DECAY
t
ENA-MEASURED
1.5V
30pF
TO
OUTPUT
PIN
50 OHMS
INPUT
OR
OUTPUT
1.5V
1.5V
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