參數(shù)資料
型號： ADSP-BF531SBST400
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號處理
英文描述： Circular Connector Series:97
中文描述： 16-BIT, 40 MHz, OTHER DSP, PQFP176
封裝： 24 X 24 MM, LQFP-176
文件頁數(shù)： 16/56頁
文件大小： 671K
代理商： ADSP-BF531SBST400
Rev. 0
|
Page 16 of 56
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March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
PIN DESCRIPTIONS
ADSP-BF531/2/3 processor pin definitions are listed in
Table 9
.
All pins are three-stated during and immediately after reset,
except the Memory Interface, Asynchronous Memory Control,
and Synchronous Memory Control pins, which are driven high.
If BR is active, then the memory pins are also three-stated. All
unused I/O pins have their input buffers disabled with the
exception of the pins that need pullups or pulldowns as noted in
the table footnotes.
In order to maintain maximum functionality and reduce pack-
age size and pin count, some pins have dual, multiplexed
functionality. In cases where pin functionality is reconfigurable,
the default state is shown in plain text, while alternate function-
ality is shown in italics.
Table 9. Pin Descriptions
Pin Name
Memory Interface
ADDR19–1
DATA15–0
ABE1–0/SDQM1–0
BR
3
BG
BGH
Asynchronous Memory Control
AMS3–0
ARDY
AOE
ARE
AWE
Synchronous Memory Control
SRAS
SCAS
SWE
SCKE
CLKOUT
SA10
SMS
Timers
TMR0
TMR1/
PPI_FS1
TMR2/
PPI_FS2
I/O Function
Driver Type
1
O
I/O Data Bus for Async/Sync Access
O
Byte Enables/Data Masks for Async/Sync Access
I
Bus Request
O
Bus Grant
O
Bus Grant Hang
Address Bus for Async/Sync Access
A
2
A
2
A
2
A
2
A
2
O
I
O
O
O
Bank Select
Hardware Ready Control
Output Enable
Read Enable
Write Enable
A
2
A
2
A
2
A
2
O
O
O
O
O
O
O
Row Address Strobe
Column Address Strobe
Write Enable
Clock Enable
Clock Output
A10 Pin
Bank Select
A
2
A
2
A
2
A
2
B
4
A
2
A
2
I/O Timer 0
I/O Timer 1/
PPI Frame Sync1
I/O Timer 2/
PPI Frame Sync2
C
5
C
5
C
5
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