參數資料
型號： ADSP-21990BSTZ
廠商： ANALOG DEVICES INC
元件分類： 數字信號處理
英文描述： High-Performance Mixed-Signal DSP, 160 MHz, 4K Words Program Memory RAM; Package: LQFP 1.4 MM; No of Pins: 176; Temperature Range: Ind
中文描述： 16-BIT, 160 MHz, OTHER DSP, PQFP176
封裝： ROHS COMPLIANT, MS-026BGA, LQFP-176
文件頁數： 8/50頁
文件大?。?/td> 2503K
代理商： ADSP-21990BSTZ
Rev. A
|
Page 16 of 50
|
August 2007
ADSP-21990
PIN FUNCTION DESCRIPTIONS
ADSP-21990 pin definitions are listed in Table 4. All
ADSP-21990 inputs are asynchronous and can be asserted asyn-
chronously to CLKIN (or to TCK for TRST).
Unused inputs should be tied or pulled to VDDEXT or GND,
except for ADDR21–0, DATA15–0, PF7-0, and inputs that have
internal pull-up or pull-down resistors (TRST, BMODE0,
BMODE1, BMODE2, BYPASS, TCK, TMS, TDI, PWMPOL,
PWMSR, and RESET)—these pins can be left floating. These
pins have a logic level hold circuit that prevents input from
floating internally. PWMTRIP has an internal pull-down, but
should not be left floating to avoid unnecessary PWM
shutdowns.
The following symbols appear in the Type column of Table 4:
G = ground, I = input, O = output, P = power supply,
B = bidirectional, T = three-state, D = digital, A = analog,
CKG = clock generation pin, PU = internal pull-up, and
PD = internal pull-down.
Table 4. Pin Descriptions
Name
Type
Function
A19-0
D, OT
External Port Address Bus
D15-0
D, BT
External Port Data Bus
RD
D, OT
External Port Read Strobe
WR
D, OT
External Port Write Strobe
ACK
D, I
External Port Access Ready Acknowledge
BR
D, I, PU
External Port Bus Request
BG
D, O
External Port Bus Grant
BGH
D, O
External Port Bus Grant Hang
MS0
D, OT
External Port Memory Select Strobe 0
MS1
D, OT
External Port Memory Select Strobe 1
MS2
D, OT
External Port Memory Select Strobe 2
MS3
D, OT
External Port Memory Select Strobe 3
IOMS
D, OT
External Port I/O Space Select Strobe
BMS
D, OT
External Port Boot Memory Select Strobe
CLKIN
D, I, CKG
Clock Input/Oscillator Input/Crystal Connection 0
XTAL
D, O, CKG
Oscillator Output/ Crystal Connection 1
CLKOUT
D, O
Clock Output (HCLK)
BYPASS
D, I, PU
PLL Bypass Mode Select
RESET
D, I, PU
Processor Reset Input
POR
D, O
Power on Reset Output
BMODE2
D, I, PU
Boot Mode Select Input 2
BMODE1
D, I, PD
Boot Mode Select Input 1
BMODE0
D, I, PU
Boot Mode Select Input 0
TCK
D, I
JTAG Test Clock
TMS
D, I, PU
JTAG Test Mode Select
TDI
D, I, PU
JTAG Test Data Input
TDO
D, OT
JTAG Test Data Output
TRST
D, I, PU
JTAG Test Reset Input
EMU
D, OT, PU
Emulation Status
VIN0
A, I
ADC Input 0
VIN1
A, I
ADC Input 1
VIN2
A, I
ADC Input 2
VIN3
A, I
ADC Input 3
VIN4
A, I
ADC Input 4
VIN5
A, I
ADC Input 5
VIN6
A, I
ADC Input 6
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