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參數(shù)資料
| 型號： | ADSP-21990BSTZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | High-Performance Mixed-Signal DSP, 160 MHz, 4K Words Program Memory RAM; Package: LQFP 1.4 MM; No of Pins: 176; Temperature Range: Ind |
| 中文描述： | 16-BIT, 160 MHz, OTHER DSP, PQFP176 |
| 封裝： | ROHS COMPLIANT, MS-026BGA, LQFP-176 |
| 文件頁數(shù)： | 49/50頁 |
| 文件大?。?/td> | 2503K |
| 代理商： | ADSP-21990BSTZ |
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Rev. A
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Page 8 of 50
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August 2007
ADSP-21990
The SCK line generates the programmed clock pulses for simul-
taneously shifting data out on MOSI and shifting data in on
MISO. In DMA mode only, transfers continue until the SPI
DMA word count transitions from 1 to 0.
In slave mode, the DSP core performs the following sequence to
set up the SPI port to receive data from a master transmitter:
Enables and configures the SPI slave port to match the
operation parameters set up on the master (data size and
transfer format) SPI transmitter.
Defines and generates a receive DMA descriptor in Page 0
of memory space to interrupt at the end of the data transfer
(optional in DMA mode only).
Enables the SPI DMA engine for a receive access (optional
in DMA mode only).
Starts receiving the data on the appropriate SCK edges after
receiving an SPI chip select on the SPISS input pin (recon-
figured programmable flag pin) from a master.
In DMA mode only, reception continues until the SPI DMA
word count transitions from 1 to 0. The DSP core could con-
tinue, by queuing up the next DMA descriptor.
Slave mode transmit operation is similar, except that the DSP
core specifies the data buffer in memory space from which to
transmit data, generates and relinquishes control of the transmit
DMA descriptor, and begins filling the SPI port data buffer. If
the SPI controller is not ready on time to transmit, it can trans-
mit a “zero” word.
DSP SERIAL PORT (SPORT)
The ADSP-21990 incorporates a complete synchronous serial
port (SPORT) for serial and multiprocessor communications.
The SPORT supports the following features:
Bidirectional: The SPORT has independent transmit and
receive sections.
Double buffered: The SPORT section (both receive and
transmit) has a data register for transferring data words to
and from other parts of the processor and a register for
shifting data in or out. The double buffering provides addi-
tional time to service the SPORT.
Clocking: The SPORT can use an external serial clock or
generate its own in a wide range of frequencies down
to 0 Hz.
Word length: Each SPORT section supports serial data
word lengths from three to 16 bits that can be transferred
either MSB first or LSB first.
Framing: Each SPORT section (receive and transmit) can
operate with or without frame synchronization signals for
each data-word; with internally generated or externally
generated frame signals; with active high or active low
frame signals; with either of two pulse widths and frame
signal timing.
Companding in hardware: Each SPORT section can per-
form A law and μ law companding according to CCITT
recommendation G.711.
Direct memory access with single cycle overhead: using the
built-in DMA master, the SPORT can automatically receive
and/or transmit multiple memory buffers of data with an
overhead of only one DSP cycle per data-word. The on-
chip DSP via a linked list of memory space resident DMA
descriptor blocks can configure transfers between the
SPORT and memory space. This chained list can be
dynamically allocated and updated.
Interrupts: Each SPORT section (receive and transmit)
generates an interrupt upon completing a data-word trans-
fer, or after transferring an entire buffer or buffers if DMA
is used.
Multichannel capability: The SPORT can receive and trans-
mit data selectively from channels of a serial bit stream that
is time division multiplexed into up to 128 channels. This is
especially useful for T1 interfaces or as a network commu-
nication scheme for multiple processors. The SPORTs also
support T1 and E1 carrier systems.
Each SPORT channel (Tx and Rx) supports a DMA buffer
of up to eight, 16-bit transfers.
The SPORT operates at a frequency of up to one-half the
clock frequency of the HCLK.
The SPORT is capable of UART software emulation.
ANALOG-TO-DIGITAL CONVERSION SYSTEM
The ADSP-21990 contains a fast, high accuracy, multiple input
analog-to-digital conversion system with simultaneous sam-
pling capabilities. This analog-to-digital conversion system
permits the fast, accurate conversion of analog signals needed in
high performance embedded systems. Key features of the ADC
system are:
14-bit pipeline (6-stage pipeline) flash analog-to-digital
converter.
8 dedicated analog inputs.
Dual-channel simultaneous sampling capability.
Programmable ADC clock rate to maximum of HCLK 4.
First channel ADC data valid approximately 375 ns after
CONVST (at 20 MSPS).
All 8 inputs converted in approximately 725 ns (at
20 MSPS).
2.0 V peak-to-peak input voltage range.
Multiple convert start sources.
Internal or external voltage reference.
Out of range detection.
DMA capable transfers from ADC to memory.
The ADC system is based on a pipeline flash converter core, and
contains dual input sample-and-hold amplifiers so that simulta-
neous sampling of two input signals is supported. The ADC
system provides an analog input voltage range of 2.0 V p-p and
provides 14-bit performance with a clock rate of up to
HCLK
4. The ADC system can be programmed to operate at
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參數(shù)描述 |
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| ADSP-21991BBC | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 150MHz 150MIPS 196-Pin Mini-BGA |
| ADSP-21991BBCZ | 功能描述:IC DSP CTLR 16BIT 196CSPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:ADSP-21xx 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
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