參數(shù)資料
型號(hào)： ADSP-2191MKCAZ-160
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 16-bit Fixed-Point DSP, 160 MIPS, 160K bytes RAM; Package: CHIP SCALE BGA; No of Pins: 144; Temperature Range: Comm.
中文描述： 16-BIT, 100 MHz, OTHER DSP, PBGA144
封裝： MINI, BGA-144
文件頁數(shù)： 15/48頁
文件大?。?/td> 1789K
代理商： ADSP-2191MKCAZ-160
ADSP-2191M
–22–
REV. A
External Port Write Cycle Timing
Table 12 and Figure 11 describe external port write operations.
The external port lets systems extend read/write accesses in three
ways: waitstates, ACK input, and combined waitstates and ACK.
To add waits with ACK, the DSP must see ACK low at the rising
edge of EMI clock. ACK low causes the DSP to wait, and the
DSP requires two EMI clock cycles after ACK goes high to finish
the access. For more information, see the External Port chapter
in the ADSP-219x/ADSP-2191 DSP Hardware Reference.
Table 12. External Port Write Cycle Timing
Parameter1, 2
Min
Max
Unit
Switching Characteristics
t
CSWS
Chip Select Asserted to
WR Asserted Delay
0.5t
HCLK –4
ns
t
AWS
Address Valid to
WR Setup and Delay
0.5t
HCLK –3
ns
t
WSCS
WR Deasserted to Chip Select Deasserted
0.5t
HCLK –4
ns
t
WSA
WR Deasserted to Address Invalid
0.5t
HCLK –3
ns
t
WW
WR Strobe Pulsewidth
t
HCLK –2+ W
3
ns
t
CDA
WR to Data Enable Access Delay
0ns
t
CDD
WR to Data Disable Access Delay
0.5t
HCLK – 3
0.5t
HCLK +4
ns
t
DSW
Data Valid to
WR Deasserted Setup
t
HCLK +1+W
3
t
HCLK +7+W
3
ns
t
DHW
WR Deasserted to Data Invalid Hold Time; E_WHC4
3.4
ns
t
DHW
WR Deasserted to Data Invalid Hold Time; E_WHC4
t
HCLK +3.4
ns
t
WWR
WR Deasserted to WR, RD Asserted
t
HCLK
Timing Requirements
t
AKW
ACK Strobe Pulsewidth
12.5
ns
t
DWSAK
ACK Delay from
WR Low
0
ns
1t
HCLK is the peripheral clock period.
2These are timing parameters that are based on worst-case operating conditions.
3W = (number of waitstates specified in wait register)
tHCLK.
4Write hold cycle–memory select control registers (MS
CTL).
Figure 11. External Port Write Cycle Timing
D 15–0
tAW S
tWW
tAKW
tDH W
tCD D
AC K
WR
A 21–0
M S 3–0
IO M S
BM S
tCSW S
tWS A
tWS C S
tCD A
tDW SA K
RD
tDS W
tWW R
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADSP-2191MKST-160 制造商:Analog Devices 功能描述:DSP 16-Bit 160MHz 160MIPS 144-Pin LQFP 制造商:Analog Devices 功能描述:Digital Signal Processor IC Supply Volta
ADSP-2191MKSTZ-160 功能描述:IC DSP CONTROLLER 16BIT 144LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:ADSP-21xx 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C，McASP，McBSP 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA
ADSP-2195MBCA-140 制造商:Analog Devices 功能描述:DSP Fixed-Point 24-Bit 140MHz 140MIPS 144-Pin CSP-BGA 制造商:Rochester Electronics LLC 功能描述:16-BIT,140 MIPS, 2.5V, 80KBYTES RAM - Bulk
ADSP-2195MBST-140 功能描述:IC DSP CONTROLLER 16BIT 144LQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:ADSP-21xx 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C，McASP，McBSP 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA
ADSP-2195MKCA-160 制造商:Analog Devices 功能描述:DSP Fixed-Point 24-Bit 160MHz 160MIPS 144-Pin CSP-BGA 制造商:Rochester Electronics LLC 功能描述:16-BIT,160 MIPS, 2.5V, 80KBYTES RAM - Bulk
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