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參數(shù)資料
| 型號： | ADSP-2189NBCA-320 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DSP Microcomputer |
| 中文描述： | 24-BIT, 40 MHz, OTHER DSP, PBGA144 |
| 封裝： | MO-205AC, BGA-144 |
| 文件頁數(shù)： | 5/32頁 |
| 文件大?。?/td> | 244K |
| 代理商： | ADSP-2189NBCA-320 |
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REV. A
ADSP-2189M
–
5
–
Table I. Interrupt Priority and Interrupt Vector Addresses
Interrupt Vector
Address (Hex)
Source Of Interrupt
RESET
(or Power-Up with PUCR = 1) 0000 (
Highest Priority
)
Power-Down (Nonmaskable)
IRQ2
IRQL1
IRQL0
SPORT0 Transmit
SPORT0 Receive
IRQE
BDMA Interrupt
SPORT1 Transmit or
IRQ1
SPORT1 Receive or
IRQ0
Timer
002C
0004
0008
000C
0010
0014
0018
001C
0020
0024
0028 (
Lowest Priority
)
Interrupt routines can either be nested with higher priority
interrupts taking precedence or processed sequentially. Inter-
rupts can be masked or unmasked with the IMASK register.
Individual interrupt requests are logically ANDed with the bits
in IMASK; the highest priority unmasked interrupt is then
selected. The power-down interrupt is nonmaskable.
The ADSP-2189M masks all interrupts for one instruction cycle
following the execution of an instruction that modifies the IMASK
register. This does not affect serial port autobuffering or DMA
transfers.
The interrupt control register, ICNTL, controls interrupt nest-
ing and defines the
IRQ0
,
IRQ1
and
IRQ2
external interrupts to
be either edge- or level-sensitive. The
IRQE
pin is an external
edge-sensitive interrupt and can be forced and cleared. The
IRQL0
and
IRQL1
pins are external level-sensitive interrupts.
The IFC register is a write-only register used to force and clear
interrupts. On-chip stacks preserve the processor status and are
automatically maintained during interrupt handling. The stacks
are twelve levels deep to allow interrupt, loop and subroutine
nesting. The following instructions allow global enable or dis-
able servicing of the interrupts (including power-down), regard-
less of the state of IMASK. Disabling the interrupts does not
affect serial port autobuffering or DMA.
ENA INTS;
DIS INTS;
When the processor is reset, interrupt servicing is enabled.
LOW POWER OPERATION
The ADSP-2189M has three low power modes that significantly
reduce the power dissipation when the device operates under
standby conditions. These modes are:
Power-Down
Idle
Slow Idle
The CLKOUT pin may also be disabled to reduce external
power dissipation.
Power-Down
The ADSP-2189M processor has a low power feature that lets
the processor enter a very low power dormant state through
hardware or software control. Here is a brief list of power-
down features. Refer to the
ADSP-2100 Family User’s Manual
,
Third Edition, “System Interface” chapter, for detailed infor-
mation about the power-down feature.
Quick recovery from power-down. The processor begins
executing instructions in as few as 200 CLKIN cycles.
Support for an externally generated TTL or CMOS proces-
sor clock. The external clock can continue running during
power-down without affecting the lowest power rating and
200 CLKIN cycle recovery.
Support for crystal operation includes disabling the oscillator
to save power (the processor automatically waits approxi-
mately 4096 CLKIN cycles for the crystal oscillator to start
or stabilize) and letting the oscillator run to allow 200 CLKIN
cycle start up.
Power-down is initiated by either the power-down pin
(
PWD
) or the software power-down force bit. Interrupt
support allows an unlimited number of instructions to be
executed before optionally powering down. The power-down
interrupt also can be used as a nonmaskable, edge-sensitive
interrupt.
Context clear/save control allows the processor to continue
where it left off or start with a clean context when leaving the
power-down state.
The
RESET
pin also can be used to terminate power-down.
Power-down acknowledge pin indicates when the processor
has entered power-down.
Idle
When the ADSP-2189M is in the Idle Mode, the processor
waits indefinitely in a low power state until an interrupt occurs.
When an unmasked interrupt occurs, it is serviced; execution
then continues with the instruction following the IDLE instruc-
tion. In Idle mode IDMA, BDMA and autobuffer cycle steals
still occur.
Slow Idle
The IDLE instruction is enhanced on the ADSP-2189M to let
the processor’s internal clock signal be slowed, further reducing
power consumption. The reduced clock frequency, a program-
mable fraction of the normal clock rate, is specified by a select-
able divisor given in the IDLE instruction.
The format of the instruction is:
IDLE (n)
;
where
n
= 16, 32, 64 or 128. This instruction keeps the proces-
sor fully functional, but operating at the slower clock rate. While
it is in this state, the processor’s other internal clock signals,
such as SCLK, CLKOUT and timer clock, are reduced by the
same ratio. The default form of the instruction, when no clock
divisor is given, is the standard
IDLE instruction.
When the IDLE (n) instruction is used, it effectively slows down
the processor’s internal clock and thus its response time to in-
coming interrupts. The one-cycle response time of the standard
idle state is increased by
n
, the clock divisor. When an enabled
interrupt is received, the ADSP-2189M will remain in the idle
state for up to a maximum of n processor cycles (
n
= 16, 32, 64,
or 128) before resuming normal operation.
When the IDLE (n) instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
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