參數(shù)資料
型號(hào)： ADSP-2187LKST-210
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： DSP Microcomputer
中文描述： 24-BIT, 26.3 MHz, OTHER DSP, PQFP100
封裝： MS-026BED, LQFP-100
文件頁(yè)數(shù)： 11/32頁(yè)
文件大小： 223K
代理商： ADSP-2187LKST-210
ADSP-2187L
–11–
REV. 0
BDMA accesses can cross page boundaries during sequential
addressing. A BDMA interrupt is generated on the completion
of the number of transfers specified by the BWCOUNT
register.
The BWCOUNT register is updated after each transfer so it can
be used to check the status of the transfers. When it reaches
zero, the transfers have finished and a BDMA interrupt is gener-
ated. The BMPAGE and BEAD registers must not be accessed
by the DSP during BDMA operations.
The source or destination of a BDMA transfer will always be
on-chip program or data memory.
When the BWCOUNT register is written with a nonzero value,
the BDMA circuit starts executing byte memory accesses with
wait states set by BMWAIT. These accesses continue until the
count reaches zero. When enough accesses have occurred to
create a destination word, it is transferred to or from on-chip
memory. The transfer takes one DSP cycle. DSP accesses to ex-
ternal memory have priority over BDMA byte memory accesses.
The BDMA Context Reset bit (BCR) controls whether or not
the processor is held off while the BDMA accesses are occur-
ring. Setting the BCR bit to 0 allows the processor to continue
operations. Setting the BCR bit to 1 causes the processor to
stop execution while the BDMA accesses are occurring, to clear
the context of the processor and start execution at address 0
when the BDMA accesses have completed.
The BDMA overlay bits specify the OVLAY memory blocks to
be accessed for internal memory.
Internal Memory DMA Port (IDMA Port; Host Memory
Mode)
The IDMA Port provides an efficient means of communication
between a host system and the ADSP-2187L. The port is used
to access the on-chip program memory and data memory of the
DSP with only one DSP cycle per word overhead. The IDMA
port cannot be used, however, to write to the DSP’s memory-
mapped control registers. A typical IDMA transfer process is
described as follows:
1. Host starts IDMA transfer.
2. Host checks
IACK
control line to see if the DSP is busy.
3. Host uses
IS
and IAL control lines to latch either the DMA
starting address (IDMAA) or the PM/DM OVLAY selection
into the DSP’s IDMA control registers.
If IAD[15] = 1, the value of IAD[7:0] represent the IDMA
overlay: IAD[14:8] must be set to 0.
If IAD[15] = 0, the value of IAD[13:0] represent the start-
ing address of internal memory to be accessed and IAD[14]
reflects PM or DM for access.
4. Host uses
IS
and
IRD
(or
IWR
) to read (or write) DSP inter-
nal memory (PM or DM).
5. Host checks IACK line to see if the DSP has completed the
previous IDMA operation.
6. Host ends IDMA transfer.
The IDMA port has a 16-bit multiplexed address and data bus
and supports 24-bit program memory. The IDMA port is
completely asynchronous and can be written to while the
ADSP-2187L is operating at full speed.
The DSP memory address is latched and then automatically in-
cremented after each IDMA transaction. An external device can
therefore access a block of sequentially addressed memory by
specifying only the starting address of the block. This increases
throughput as the address does not have to be sent for each
memory access.
IDMA Port access occurs in two phases. The first is the IDMA
Address Latch cycle. When the acknowledge is asserted, a
14-bit address and 1-bit destination type can be driven onto the
bus by an external device. The address specifies an on-chip
memory location; the destination type specifies whether it is a
DM or PM access. The falling edge of the address latch signal
latches this value into the IDMAA register.
Once the address is stored, data can either be read from or
written to the ADSP-2187L’s on-chip memory. Asserting the
select line (
IS
) and the appropriate read or write line (
IRD
and
IWR
respectively) signals the ADSP-2187L that a particular
transaction is required. In either case, there is a one-processor-
cycle delay for synchronization. The memory access consumes
one additional processor cycle.
Once an access has occurred, the latched address is automati-
cally incremented and another access can occur.
Through the IDMAA register, the DSP can also specify the
starting address and data format for DMA operation. Asserting
the IDMA port select (IS) and address latch enable (IAL) di-
rects the ADSP-2187L to write the address onto the IAD0–14
bus into the IDMA Control Register. If IAD[15] is set to 0,
IDMA latches the address. If IAD[15] is set to 1, IDMA
latches OVLAY memory. The IDMA OVLAY and address are
stored in separate memory-mapped registers. The IDMAA regis-
ter, shown below, is memory mapped at address DM (0x3FE0).
Note that the latched address (IDMAA) cannot be read back by
the host. The IDMA OVLAY register is memory mapped at
address DM (0x3FE7). See Figures 8 and 9 for more informa-
tion on IDMA and DMA memory maps.
IDMA CONTROL (U = UNDEFINED AT RESET)
15 14 13 12 11 10
9
DM(0
3
3FE0)
IDMAA
ADDRESS
IDMAD
DESTINATION MEMORY TYPE:
0 = PM
1 = DM
IDMA OVERLAY
9
8
DM(0
3
3FE7)
RESERVED
SET TO 0
ID DMOVLAY
ID PMOVLAY
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15 14 13 12 11 10
7
6
5
4
3
2
1
0
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
8
7
6
5
4
3
2
1
0
Figure 8. IDMA Control/OVLAY Registers
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