參數(shù)資料
型號(hào)： ADSP-21363SBBCZENG
廠(chǎng)商： ANALOG DEVICES INC
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： SHARC Processor
中文描述： 16-BIT, 55.55 MHz, OTHER DSP, PBGA136
封裝： LEAD FREE, MO-205AE, MBGA-136
文件頁(yè)數(shù)： 18/44頁(yè)
文件大?。?/td> 396K
代理商： ADSP-21363SBBCZENG
Rev. PrA
|
Page 18 of 44
|
September 2004
ADSP-21363
Preliminary Technical Data
Clock Input
Clock Signals
The ADSP-21363 can use an external clock or a crystal. See
CLKIN pin description in
Table 3 on Page 10
. The programmer
can configure the ADSP-21363 to use its internal clock genera-
tor by connecting the necessary components to CLKIN and
XTAL.
Figure 8
shows the component connections used for a
crystal operating in fundamental mode. Note that the clock rate
is achieved using a 16.67 MHz crystal and a PLL multiplier ratio
16:1 (CCLK:CLKIN achieves a clock speed of 266 MHz). To
achieve the full core clock rate, programs need to configure the
multiplier bits in the PMCTL register.
Table 11. Clock Input
Parameter
333 MHz
Unit
Min
Max
Timing Requirements
t
CK
t
CKL
t
CKH
t
CKRF
t
CCLK
3
CLKIN Period
CLKIN Width Low
CLKIN Width High
CLKIN Rise/Fall (0.4V–2.0V)
CCLK Period
18
1
7.5
1
7.5
1
3.0
1
1
Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in PMCTL.
2
Applies only for CLKCFG1–0 = 01 and default values for PLL control bits in PMCTL.
3
Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t
CCLK
.
TBD
2
TBD
2
TBD
2
TBD
TBD
ns
ns
ns
ns
ns
Figure 7. Clock Input
CLKIN
t
CK
t
CKH
t
CKL
Figure 8. 333 MHz Operation (Fundamental Mode Crystal)
CLKIN
XTAL
C1
C2
X1
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. CRYSTAL
SELECTION MUST COMPLY WITH CLKCFG1-0 = 10 OR = 01.
1M
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