參數(shù)資料
型號(hào)： ADSP-21363SBBC-ENG
廠商： ANALOG DEVICES INC
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： SHARC Processor
中文描述： 16-BIT, 55.55 MHz, OTHER DSP, PBGA136
封裝： MO-205AE, MBGA-136
文件頁(yè)數(shù)： 28/44頁(yè)
文件大小： 396K
代理商： ADSP-21363SBBC-ENG
Rev. PrA
|
Page 28 of 44
|
September 2004
ADSP-21363
Preliminary Technical Data
Serial Ports
To determine whether communication is possible between two
devices at clock speed n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,
2) data delay and data setup and hold, and 3) SCLK width.
Serial port signals (SCLK, FS, DxA,/DxB) are routed to the
DAI_P20–1 pins using the SRU. Therefore, the timing specifica-
tions provided below are valid at the DAI_P20–1 pins.
Table 24. Serial Ports—External Clock
Parameter
Timing Requirements
t
SFSE
1
Min
Max
Unit
FS Setup Before SCLK
(Externally Generated FS in either Transmit or Receive Mode)
FS Hold After SCLK
(Externally Generated FS in either Transmit or Receive Mode)
Receive Data Setup Before Receive SCLK
Receive Data Hold After SCLK
SCLK Width
SCLK Period
2.5
ns
t
HFSE
1
2.5
2.5
2.5
24
48
ns
ns
ns
ns
ns
t
SDRE
1
t
HDRE
1
t
SCLKW
t
SCLK
Switching Characteristics
t
DFSE
2
FS Delay After SCLK
(Internally Generated FS in either Transmit or Receive Mode)
FS Hold After SCLK
(Internally Generated FS in either Transmit or Receive Mode)
Transmit Data Delay After Transmit SCLK
Transmit Data Hold After Transmit SCLK
7
ns
t
HOFSE
2
2
ns
ns
ns
t
DDTE
2
t
HDTE
2
1
Referenced to sample edge.
2
Referenced to drive edge.
7
2
Table 25. Serial Ports—Internal Clock
Parameter
Timing Requirements
t
SFSI
1
Min
Max
Unit
FS Setup Before SCLK
(Externally Generated FS in either Transmit or Receive Mode)
FS Hold After SCLK
(Externally Generated FS in either Transmit or Receive Mode)
Receive Data Setup Before SCLK
Receive Data Hold After SCLK
7
ns
t
HFSI
1
2.5
7
2.5
ns
ns
ns
t
SDRI
1
t
HDRI
1
Switching Characteristics
t
DFSI
2
t
HOFSI
2
t
DFSI
2
t
HOFSI
2
t
DDTI
2
t
HDTI
2
t
SCLKIW
1
Referenced to the sample edge.
2
Referenced to drive edge.
FS Delay After SCLK (Internally Generated FS in Transmit Mode)
FS Hold After SCLK (Internally Generated FS in Transmit Mode)
FS Delay After SCLK (Internally Generated FS in Receive or Mode)
FS Hold After SCLK (Internally Generated FS in Receive Mode)
Transmit Data Delay After SCLK
Transmit Data Hold After SCLK
Transmit or Receive SCLK Width
3
ns
ns
ns
ns
ns
ns
ns
–1.0
3
–1.0
3
–1.0
0.5t
SCLK
– 2
0.5t
SCLK
+ 2
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