參數(shù)資料
型號(hào)： ADSP-21065LKCAZ264
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 10/44頁(yè)
文件大?。?/td> 0K
描述： IC DSP CTLR 32BIT 196CSPBGA
產(chǎn)品培訓(xùn)模塊： SHARC Processor Overview
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類型： 浮點(diǎn)
接口： 主機(jī)接口，串行端口
時(shí)鐘速率： 60MHz
非易失內(nèi)存： 外部
芯片上RAM： 64kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 3.30V
工作溫度： 0°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 196-BGA，CSPBGA
供應(yīng)商設(shè)備封裝： 196-CSPBGA（15x15）
包裝： 托盤
REV. C
ADSP-21065L
–18–
Synchronous Read/Write—Bus Master
Use these specifications for interfacing to external memory systems that require CLKIN-relative timing or for accessing a slave
ADSP-21065L (in multiprocessor memory space). These synchronous switching characteristics are also valid during asynchronous
memory reads and writes (see Memory Read—Bus Master and Memory Write—Bus Master).
When accessing a slave ADSP-21065L, these switching characteristics must meet the slave’s timing requirements for synchronous
read/writes (see Synchronous Read/Write—Bus Slave). The slave ADSP-21065L must also meet these (bus master) timing require-
ments for data and acknowledge setup and hold times.
Parameter
Min
Max
Unit
Timing Requirements:
tSSDATI
Data Setup Before CLKIN
0.25 + 2 DT
ns
tHSDATI
Data Hold After CLKIN
4.0 – 2 DT
ns
tDAAK
ACK Delay After Address,
MSx, SW, BMS1, 2
24.0 + 30 DT + W
ns
tSACKC
ACK Setup Before CLKIN
1
2.75 + 4 DT
ns
tHACK
ACK Hold After CLKIN
2.0 – 4 DT
ns
Switching Characteristics:
tDADRO
Address,
MSx, BMS, SW Delay After CLKIN1
7.0 – 2 DT
ns
tHADRO
Address,
MSx, BMS, SW Hold After CLKIN
0.5 – 2 DT
ns
tDRDO
RD High Delay After CLKIN
0.5 – 2 DT
6.0 – 2 DT
ns
tDWRO
WR High Delay After CLKIN
0.0 – 3 DT
6.0 – 3 DT
ns
tDRWL
RD/WR Low Delay After CLKIN
7.5 + 4 DT
11.75 + 4 DT
ns
tDDATO
Data Delay After CLKIN
22.0 + 10 DT
ns
tDATTR
Data Disable After CLKIN
3
1.0 – 2 DT
7.0 – 2 DT
ns
tDBM
BMSTR Delay After CLKIN
3.0
ns
tHBM
BMSTR Hold After CLKIN
–4.0
ns
W = (number of wait states specified in WAIT register)
tCK.
NOTES
1Data Hold: User must meet t
HDA or tHDRH or synchronous specification tHDATI. See system hold time calculation under test conditions for the calculation of hold
times given capacitive and dc loads.
2ACK is not sampled on external memory accesses that use the Internal wait state mode. For the first CLKIN cycle of a new external memory access, ACK must be
valid by tDAAK or tDSAK or synchronous specification tSACKC for wait state modes External, Either, or Both (Both, if the internal wait state is zero). For the second and
subsequent cycles of a wait stated external memory access, synchronous specifications t SACKC and tHACKC must be met for wait state modes External, Either, or Both
(Both, after internal wait states have completed).
3See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
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