參數(shù)資料
型號(hào)： ADSP-21062LKS-133
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： ADSP-2106x SHARC DSP Microcomputer Family
中文描述： 48-BIT, 33.33 MHz, OTHER DSP, PQFP240
封裝： MS-029GA, MQFP-240
文件頁數(shù)： 31/48頁
文件大小： 370K
代理商： ADSP-21062LKS-133
ADSP-21062/ADSP-21062L
–31–
REV. C
transfer is controlled by ADDR31-0,
RD
,
WR
,
MS
3-0
, and ACK
(not
DMAG
). For Paced Master mode, the Memory Read–Bus
Master, Memory Write–Bus Master, and Synchronous Read/
Write–Bus Master timing specifications for ADDR
31-0
,
RD
,
WR
,
MS
3-0
,
SW
, PAGE, DATA47-0, and ACK also apply.
ADSP-21062
Min
ADSP-21062L
Min
Parameter
Max
Max
Units
Timing Requirements:
t
SDRLC
t
SDRHC
t
WDR
DMAR
x Low Setup Before CLKIN
1
DMAR
x High Setup Before CLKIN
1
DMAR
x Width Low
(Nonsynchronous)
t
SDATDGL
Data Setup After
DMAG
x Low
2
t
HDATIDG
Data Hold After
DMAG
x High
t
DATDRH
Data Valid After
DMAR
x High
2
t
DMARLL
DMAR
x Low Edge to Low Edge
t
DMARH
DMAR
x Width High
5
5
5
5
ns
ns
6
6
ns
ns
ns
ns
ns
ns
10 + 5DT/8
10 + 5DT/8
2
2
16 + 7DT/8
16 + 7DT/8
23 + 7DT/8
6
23 + 7DT/8
6
Switching Characteristics:
t
DDGL
DMAG
x Low Delay After CLKIN
t
WDGH
DMAG
x High Width
t
WDGL
DMAG
x Low Width
t
HDGC
DMAG
x High Delay After CLKIN
t
VDATDGH
Data Valid Before
DMAG
x High
3
t
DATRDGH
Data Disable After
DMAG
x High
4
t
DGWRL
WR
Low Before
DMAG
x Low
t
DGWRH
DMAG
x Low Before
WR
High
t
DGWRR
WR
High Before
DMAG
x High
t
DGRDL
RD
Low Before
DMAG
x Low
t
DRDGH
RD
Low Before
DMAG
x High
t
DGRDR
RD
High Before
DMAG
x High
t
DGWR
DMAG
x High to
WR
,
RD
,
DMAG
x
Low
t
DADGH
Address/Select Valid to
DMAG
x High
t
DDGHA
Address/Select Hold after
DMAG
x
High
9 + DT/4
6 + 3DT/8
12 + 5DT/8
–2 – DT/8
8 + 9DT/16
0
–0.25
10 + 5DT/8 + W
1 + DT/16
0
11 + 9DT/16 + W
0
15 + DT/4
9 + DT/4
6 + 3DT/8
12 + 5DT/8
–2 – DT/8
8 + 9DT/16
0
–0.25
10 + 5DT/8 + W
1 + DT/16
0
11 + 9DT/16 + W
0
15 + DT/4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6 – DT/8
6 – DT/8
7
2
7
2
3 + DT/16
2
3 + DT/16
2
3
3
5 + 3DT/8 + HI
17 + DT
5 + 3DT/8 + HI
17 + DT
ns
ns
–0.5
–1
ns
W = (number of wait states specified in WAIT register)
×
t
CK
.
HI = t
CK
(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
NOTES
1
Only required for recognition in the current cycle.
2
t
SDATDGL
is the data setup requirement if
DMAR
x is not being used to hold off completion of a write. Otherwise, if
DMAR
x low holds off completion of the write, the
data can be driven t
DATDRH
after
DMAR
x is brought high.
3
t
VDATDGH
is valid if
DMAR
x is not being used to hold off completion of a read. If
DMAR
x is used to prolong the read, then t
VDATDGH
= 8 + 9DT/16 + (n
×
t
CK
) where
n
equals the number of extra cycles that the access is prolonged.
4
See
System Hold Time Calculation
under Test Conditions for calculation of hold times given capacitive and dc loads.
DMA Handshake
These specifications describe the three DMA handshake modes.
In all three modes DMAR is used to initiate transfers. For hand-
shake mode, DMAG controls the latching or enabling of data
externally. For external handshake mode, the data transfer is
controlled by the ADDR
31-0
,
RD
,
WR
,
SW
, PAGE,
MS
3-0
,
ACK, and
DMAG
signals. For Paced Master mode, the data
相關(guān)PDF資料
PDF描述
ADSP-21062LKS-160 ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21062LCS-160 ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21062LAB-160 ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21062KB-160 ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21062 ADSP-2106x SHARC DSP Microcomputer Family
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ADSP-21065 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer
ADSP-21065L 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer
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