參數(shù)資料
型號: ADSP-21062LCS-160
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號處理
英文描述: ADSP-2106x SHARC DSP Microcomputer Family
中文描述: 48-BIT, 40 MHz, OTHER DSP, PQFP240
封裝: MS-029GA, MQFP-240
文件頁數(shù): 20/48頁
文件大?。?/td> 370K
代理商: ADSP-21062LCS-160
–20–
ADSP-21062/ADSP-21062L
REV. C
ADSP-21062
Min
ADSP-21062L
Min
Parameter
Max
Max
Units
Timing Requirements:
t
DAD
Address, Selects Delay to Data Valid
1, 4
t
DRLD
RD
Low to Data Valid
1
t
HDA
Data Hold from Address, Selects
2
t
HDRH
Data Hold from
RD
High
2
t
DAAK
ACK Delay from Address, Selects
3, 4
t
DSAK
ACK Delay from
RD
Low
3
18 + DT + W
12 + 5DT/8 + W
18 + DT + W
12 + 5DT/8 + W
ns
ns
ns
ns
ns
ns
0.5
2.0
0.5
2.0
14 + 7DT/8 + W
8 + DT/2 + W
14 + 7DT/8 + W
8 + DT/2 + W
Switching Characteristics:
t
DRHA
Address, Selects Hold After
RD
High
t
DARL
Address, Selects to
RD
Low
4
t
RW
RD
Pulsewidth
t
RWR
RD
High to
WR
,
RD
,
DMAG
x Low
t
SADADC
Address, Selects Setup Before
ADRCLK High
4
0 + H
2 + 3DT/8
12.5 + 5DT/8 + W
8 + 3DT/8 + HI
0 + H
2 + 3DT/8
12.5 + 5DT/8 + W
8 + 3DT/8 + HI
ns
ns
ns
ns
0 + DT/4
0 + DT/4
ns
W = (number of wait states specified in WAIT register)
×
t
CK.
HI = t
CK
(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
H = t
CK
(if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
NOTES
1
Data Delay/Setup: User must meet t
DAD
or t
or synchronous spec t
.
2
Data Hold: User must meet t
HDA
or t
HDRH
or synchronous spec t
HSDATI
. See
System Hold Time Calculatio
n under Test Conditions for the calculation of hold times
given capacitive and dc loads.
3
ACK Delay/Setup: User must meet t
DAAK
or t
DSAK
or synchronous specification t
SACKC
for deassertion of ACK (Low), all three specifications must be met for asser-
tion of ACK (High).
4
The falling edge of
MS
x,
SW
,
BMS
is referenced.
WR
,
DMAG
ACK
DATA
RD
ADDRESS
MS
x,
SW
BMS
t
DARL
t
RW
t
DAD
t
SADADC
t
DAAK
t
HDRH
t
HDA
t
RWR
t
DRLD
ADRCLK
(OUT)
t
DRHA
t
DSAK
Figure 13. Memory Read—Bus Master
Memory Read—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-21062 is
the bus master accessing external memory space. These switching
characteristics also apply for bus master synchronous read/write
timing (see Synchronous Read/Write – Bus Master below). If
these timing requirements are met, the synchronous read/write
timing can be ignored (and vice versa).
相關(guān)PDF資料
PDF描述
ADSP-21062LAB-160 ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21062KB-160 ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21062 ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21062L Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection
ADSP-21062LKB-160 ADSP-2106x SHARC DSP Microcomputer Family
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