參數(shù)資料
型號(hào)： ADSP-21060KS-160
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： ADSP-2106x SHARC DSP Microcomputer Family
中文描述： 48-BIT, 40 MHz, OTHER DSP, PQFP240
封裝： MS-029GA, MQFP-240
文件頁(yè)數(shù)： 9/47頁(yè)
文件大?。?/td> 366K
代理商： ADSP-21060KS-160
ADSP-21060/ADSP-21060L
–9–
REV. D
Pin
Type
Function
SBTS
I/S
Suspend Bus Three-State
. External devices can assert
SBTS
(low) to place the external bus address,
data, selects and strobes in a high impedance state for the following cycle. If the ADSP-2106x
attempts to access external memory while
SBTS
is asserted, the processor will halt and the memory
access will not be completed until
SBTS
is deasserted.
SBTS
should only be used to recover from host
processor/ADSP-2106x deadlock, or used with a DRAM controller.
Interrupt Request Lines
. May be either edge-triggered or level-sensitive.
Flag Pins
. Each is configured via control bits as either an input or output. As an input, it can be
tested as a condition. As an output, it can be used to signal external peripherals.
Timer Expired
. Asserted for four cycles when the timer is enabled and TCOUNT decrements to
zero.
Host Bus Request
. Must be asserted by a host processor to request control of the ADSP-2106x’s
external bus. When
HBR
is asserted in a multiprocessing system, the ADSP-2106x that is bus master
will relinquish the bus and assert
HBG
. To relinquish the bus, the ADSP-2106x places the address,
data, select and strobe lines in a high impedance state.
HBR
has priority over all ADSP-2106x bus
requests (
BR
6-1
) in a multiprocessing system.
Host Bus Grant
. Acknowledges an
HBR
bus request, indicating that the host processor may take
control of the external bus.
HBG
is asserted (held low) by the ADSP-2106x until
HBR
is released. In a
multiprocessing system,
HBG
is output by the ADSP-2106x bus master and is monitored by all others.
Chip Select
. Asserted by host processor to select the ADSP-2106x.
Host Bus Acknowledge
. The ADSP-2106x deasserts REDY (low) to add wait states to an asynchro-
nous access of its internal memory or IOP registers by a host. Open drain output (O/D) by default; can
be programmed in ADREDY bit of SYSCON register to be active drive (A/D). REDY will only be
output if the
CS
and
HBR
inputs are asserted.
DMA Request 1
(DMA Channel 7).
DMA Request 2
(DMA Channel 8).
DMA Grant 1
(DMA Channel 7).
DMA Grant 2
(DMA Channel 8).
Multiprocessing Bus Requests
. Used by multiprocessing ADSP-2106xs to arbitrate for bus master-
ship. An ADSP-2106x only drives its own
BR
x line (corresponding to the value of its ID
2-0
inputs) and
monitors all others. In a multiprocessor system with less than six ADSP-2106xs, the unused
BR
x pins
should be pulled high; the processor’s own
BR
x line must not be pulled high or low because it is an
output.
Multiprocessing ID
. Determines which multiprocessing bus request (
BR1
–
BR6
) is used by ADSP-
2106x. ID = 001 corresponds to
BR1
, ID = 010 corresponds to
BR2
, etc. ID = 000 in single-processor
systems. These lines are a system configuration selection which should be hardwired or only changed
at reset.
Rotating Priority Bus Arbitration Select
. When RPBA is high, rotating priority for multiprocessor
bus arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system con-
figuration selection which must be set to the same value on every ADSP-2106x. If the value of RPBA is
changed during system operation, it must be changed in the same CLKIN cycle on every ADSP-2106x.
Core Priority Access
. Asserting its
CPA
pin allows the core processor of an ADSP-2106x bus slave
to interrupt background DMA transfers and gain access to the external bus.
CPA
is an open drain
output that is connected to all ADSP-2106xs in the system. The
CPA
pin has an internal 5 k
pull-up
resistor. If core access priority is not required in a system, the
CPA
pin should be left unconnected.
Data Transmit
(Serial Ports 0, 1). Each DT pin has a 50 k
internal pull-up resistor.
Data Receive
(Serial Ports 0, 1). Each DR pin has a 50 k
internal pull-up resistor.
Transmit Clock
(Serial Ports 0, 1). Each TCLK pin has a 50 k
internal pull-up resistor.
Receive Clock
(Serial Ports 0, 1). Each RCLK pin has a 50 k
internal pull-up resistor.
IRQ
2-0
FLAG
3-0
I/A
I/O/A
TIMEXP
O
HBR
I/A
HBG
I/O
CS
REDY (O/D) O
I/A
DMAR1
DMAR2
DMAG1
DMAG2
BR
6-1
I/A
I/A
O/T
O/T
I/O/S
ID
2-0
I
RPBA
I/S
CPA
(O/D)
I/O
DTx
DRx
TCLKx
RCLKx
O
I
I/O
I/O
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