參數(shù)資料
型號(hào): ADSP-21060KS-133
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號(hào)處理
英文描述: ADSP-2106x SHARC DSP Microcomputer Family
中文描述: 48-BIT, 33.33 MHz, OTHER DSP, PQFP240
封裝: MS-029GA, MQFP-240
文件頁(yè)數(shù): 22/47頁(yè)
文件大?。?/td> 366K
代理商: ADSP-21060KS-133
–22–
ADSP-21060/ADSP-21060L
REV. D
ADSP-21060
Min
ADSP-21060L
Min
Parameter
Max
Max
Units
Timing Requirements:
t
SSDATI
Data Setup before CLKIN
t
HSDATI
Data Hold after CLKIN
t
DAAK
ACK Delay after Address,
MS
x,
SW
,
BMS
1, 2
t
SACKC
ACK Setup before CLKIN
2
t
HACK
ACK Hold after CLKIN
3 + DT/8
3.5 – DT/8
3 + DT/8
3.5 – DT/8
ns
ns
14 + 7 DT/8 + W
14 + 7 DT/8 + W
ns
ns
ns
6.5 + DT/4
–1 – DT/4
6.5 + DT/4
–1 – DT/4
Switching Characteristics:
t
DADRO
Address,
MS
x,
BMS
,
SW
Delay
after CLKIN
1
t
HADRO
Address,
MS
x,
BMS
,
SW
Hold
after CLKIN
t
DPGC
PAGE Delay after CLKIN
t
DRDO
RD
High Delay after CLKIN
t
DWRO
WR
High Delay after CLKIN
t
DRWL
RD
/
WR
Low Delay after CLKIN
t
SDDATO
Data Delay after CLKIN
t
DATTR
Data Disable after CLKIN
3
t
DADCCK
ADRCLK Delay after CLKIN
t
ADRCK
ADRCLK Period
t
ADRCKH
ADRCLK Width High
t
ADRCKL
ADRCLK Width Low
7 – DT/8
7 – DT/8
ns
–1 – DT/8
9 + DT/8
–2 – DT/8
–3 – 3DT/16
8 + DT/4
–1 – DT/8
9 + DT/8
–2 – DT/8
–3 – 3DT/16
8 + DT/4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
16 + DT/8
4 – DT/8
4 – 3DT/16
12.5 + DT/4
19 + 5DT/16
7 – DT/8
10 + DT/8
16 + DT/8
4 – DT/8
4 – 3DT/16
12.5 + DT/4
19 + 5DT/16
7 – DT/8
10 + DT/8
0 – DT/8
4 + DT/8
t
CK
(t
CK
/2) – 2
(t
CK
/2) – 2
0 – DT/8
4 + DT/8
t
CK
(t
CK
/2) – 2
(t
CK
/2) – 2
W = (number of Wait states specified in WAIT register)
×
t
CK
.
NOTES
1
The falling edge of
MS
x,
SW
,
BMS
is referenced.
2
ACK Delay/Setup: User must meet t
DAAK
or t
DSAK
or synchronous specification t
SACKC
for deassertion of ACK (Low), all three specifications must be met for assertion
of ACK (High).
3
See
System Hold Time Calculation
under Test Conditions for calculation of hold times given capacitive and dc loads.
Synchronous Read/Write—Bus Master
Use these specifications for interfacing to external memory
systems that require CLKIN—relative timing or for accessing a
slave ADSP-2106x (in multiprocessor memory space). These
synchronous switching characteristics are also valid during asyn-
chronous memory reads and writes (see Memory Read—Bus
Master and Memory Write—Bus Master).
When accessing a slave ADSP-2106x, these switching character-
istics must meet the slave’s timing requirements for synchronous
read/writes (see Synchronous Read/Write—Bus Slave). The
slave ADSP-2106x must also meet these (bus master) timing
requirements for data and acknowledge setup and hold times.
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ADSP-21060KS-160 ADSP-2106x SHARC DSP Microcomputer Family
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