參數(shù)資料
型號(hào)： ADSP-21060KS-133
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： ADSP-2106x SHARC DSP Microcomputer Family
中文描述： 48-BIT, 33.33 MHz, OTHER DSP, PQFP240
封裝： MS-029GA, MQFP-240
文件頁(yè)數(shù)： 10/47頁(yè)
文件大?。?/td> 366K
代理商： ADSP-21060KS-133
–10–
ADSP-21060/ADSP-21060L
REV. D
Pin
Type
Function
TFSx
RFSx
LxDAT
3-0
I/O
I/O
I/O
Transmit Frame Sync
(Serial Ports 0, 1).
Receive Frame Sync
(Serial Ports 0, 1).
Link Port Data
(Link Ports 0–5). Each LxCLK pin has a 50 k
internal pull-down resistor that is
enabled or disabled by the LPDRD bit of the LCOM register.
Link Port Clock
(Link Ports 0–5). Each LxCLK pin has a 50 k
internal pull-down resistor that is
enabled or disabled by the LPDRD bit of the LCOM register.
Link Port Acknowledge
(Link Ports 0–5). Each LxACK pin has a 50 k
internal pull-down resistor
that is enabled or disabled by the LPDRD bit of the LCOM register.
EPROM Boot Select
. When EBOOT is high, the ADSP-2106x is configured for booting from an 8-
bit EPROM. When EBOOT is low, the LBOOT and
BMS
inputs determine booting mode. See table
below. This signal is a system configuration selection that should be hardwired.
Link Boot
. When LBOOT is high, the ADSP-2106x is configured for link port booting. When
LBOOT is low, the ADSP-2106x is configured for host processor booting or no booting. See table
below. This signal is a system configuration selection that should be hardwired.
Boot Memory Select
.
Output
: Used as chip select for boot EPROM devices (when EBOOT= 1,
LBOOT = 0). In a multiprocessor system,
BMS
is output by the bus master.
Input:
When low, indi-
cates that no booting will occur and that ADSP-2106x will begin executing instructions from external
memory. See table below. This input is a system configuration selection that should be hardwired.
*Three-statable only in EPROM boot mode (when
BMS
is an output).
EBOOT
LBOOT
BMS
Booting Mode
1
0
Output
EPROM (Connect
BMS
to EPROM chip select.)
0
0
1 (Input)
Host Processor
0
1
1 (Input)
Link Port
0
0
0 (Input)
No Booting. Processor executes from external memory.
0
1
0 (Input)
Reserved
1
1
x (Input)
Reserved
Clock In
. External clock input to the ADSP-2106x. The instruction cycle rate is equal to CLKIN.
CLKIN may not be halted, changed, or operated below the minimum specified frequency.
Processor Reset
. Resets the ADSP-2106x to a known state and begins execution at the program
memory location specified by the hardware reset vector address. This input must be asserted (low) at
power-up.
Test Clock (JTAG)
. Provides an asynchronous clock for JTAG boundary scan.
Test Mode Select (JTAG)
. Used to control the test state machine. TMS has a 20 k
internal pull-up
resistor.
Test Data Input (JTAG)
. Provides serial data for the boundary scan logic. TDI has a 20 k
internal
pull-up resistor.
Test Data Output (JTAG)
. Serial scan output of the boundary scan path.
Test Reset (JTAG)
. Resets the test state machine.
TRST
must be asserted (pulsed low) after power-
up or held low for proper operation of the ADSP-2106x.
TRST
has a 20 k
internal pull-up resistor.
Emulation Status
. Must be connected to the ADSP-2106x EZ-ICE target board connector
only
.
Reserved
, leave unconnected.
Power Supply
; nominally +5.0 V dc for 5 V devices or +3.3 V dc for 3.3 V devices. (30 pins).
Power Supply Return
. (30 pins).
Do Not Connect
. Reserved pins which must be left open and unconnected.
LxCLK
I/O
LxACK
I/O
EBOOT
I
LBOOT
I
BMS
I/O/T*
CLKIN
I
RESET
I/A
TCK
TMS
I
I/S
TDI
I/S
TDO
TRST
O
I/A
EMU
(O/D)
ICSA
VDD
GND
NC
O
O
P
G
相關(guān)PDF資料
PDF描述
ADSP-21060KS-160 ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21060LKB-160 RES, 2.2 K SM CHIP 5% 50V 1/16 WATT, 0603
ADSP-21060LKS-133 ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21060LKS-160 ADSP-2106x SHARC DSP Microcomputer Family
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADSP-21060KS-160 功能描述:IC DSP CONTROLLER 32BIT 240MQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤
ADSP-21060KSZ-133 功能描述:IC DSP CONTROLLER 32BIT 240-MQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤
ADSP-21060KSZ-160 功能描述:IC DSP CONTROLLER 32BIT 240MQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C，McASP，McBSP 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA
ADSP21060L 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP MICROCOMPUTER
ADSP-21060L 制造商:AD 制造商全稱:Analog Devices 功能描述:ADSP-2106x SHARC DSP Microcomputer Family
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