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參數(shù)資料
| 型號： | ADSP-2104LKP-55 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Low Cost DSP Microcomputers |
| 中文描述： | 24-BIT, 13.824 MHz, OTHER DSP, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 8/36頁 |
| 文件大?。?/td> | 333K |
| 代理商： | ADSP-2104LKP-55 |
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ADSP-2104/ADSP-2109
–8–
REV. 0
Boot Memory Interface
Boot memory is an external 16K by 8 space, divided into eight
separate 2K by 8 pages. T he 8-bit bytes are automatically
packed into 24-bit instruction words by the processor, for
loading into on-chip program memory.
T hree bits in the processors’ System Control Register select
which page is loaded by the boot memory interface. Another bit
in the System Control Register allows the forcing of a boot
loading sequence under software control. Boot loading from
Page 0 after
RESET
is initiated automatically if MMAP = 0.
T he boot memory interface can generate zero to seven wait
states; it defaults to three wait states after
RESET
. T his allows
the ADSP-2104 to boot from a single low cost EPROM such as
a 27C256. Program memory is booted one byte at a time and
converted to 24-bit program memory words.
T he
BMS
and
RD
signals are used to select and to strobe the
boot memory interface. Only 8-bit data is read over the data
bus, on pins D8-D15. T o accommodate up to eight pages of
boot memory, the two MSBs of the data bus are used in the
boot memory interface as the two MSBs of the boot memory
address: D23, D22, and A13 supply the boot page number.
T he ADSP-2100 Family Assembler and Linker allow the
creation of programs and data structures requiring multiple boot
pages during execution.
T he
BR
signal is recognized during the booting sequence. T he
bus is granted after loading the current byte is completed.
BR
during booting may be used to implement booting under control
of a host processor.
Bus Interface
T he ADSP-2104/ADSP-2109 can relinquish control of their
data and address buses to an external device. When the external
device requires control of the buses, it asserts the bus request
signal (
BR
). If the processor is not performing an external
memory access, it responds to the active
BR
input in the next
cycle by:
T hree-stating the data and address buses and the
PMS
,
DMS
,
BMS
,
RD
,
WR
output drivers,
Asserting the bus grant (
BG
) signal,
and halting program execution.
If the Go mode is set, however, the ADSP-2104/ADSP-2109
will not halt program execution until it encounters an instruc-
tion that requires an external memory access.
If the processor is performing an external memory access when
the external device asserts the
BR
signal, it will not three-state
the memory interfaces or assert the
BG
signal until the cycle
after the access completes (up to eight cycles later depending on
the number of wait states). T he instruction does not need to be
completed when the bus is granted; the processor will grant the
bus in between two memory accesses if an instruction requires
more than one external memory access.
When the
BR
signal is released, the processor releases the
BG
signal, re-enables the output drivers and continues program
execution from the point where it stopped.
T he bus request feature operates at all times, including when
the processor is booting and when
RESET
is active. If this
feature is not used, the
BR
input should be tied high (to V
DD
).
Low Power IDLE Instruction
T he IDLE instruction places the processor in low power state in
which it waits for an interrupt. When an interrupt occurs, it is
serviced and execution continues with instruction following
IDLE. T ypically this next instruction will be a JUMP back to
the IDLE instruction. T his implements a low-power standby
loop.
T he
IDLE n
instruction is a special version of IDLE that slows
the processor’s internal clock signal to further reduce power
consumption. T he reduced clock frequency, a programmable
fraction of the normal clock rate, is specified by a selectable
divisor,
n
, given in the IDLE instruction. T he syntax of the
instruction is:
IDLE n
;
where
n
= 16, 32, 64, or 128.
T he instruction leaves the chip in an idle state, operating at the
slower rate. While it is in this state, the processor’s other
internal clock signals, such as SCLK , CLK OUT , and the timer
clock, are reduced by the same ratio. Upon receipt of an
enabled interrupt, the processor will stay in the IDLE state for
up to a maximum of
n
CLK IN cycles, where
n
is the divisor
specified in the instruction, before resuming normal operation.
When the
IDLE n
instruction is used, it slows the processor’s
internal clock and thus its response time to incoming interrupts–
the 1-cycle response time of the standard IDLE state is in-
creased by
n
, the clock divisor. When an enabled interrupt is
received, the ADSP-21xx will remain in the IDLE state for up
to a maximum of
n
CLK IN cycles (where
n
= 16, 32, 64, or
128) before resuming normal operation.
When the
IDLE n
instruction is used in systems that have an
externally generated serial clock (SCLK ), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
faster rate than can be serviced, due to the additional time the
processor takes to come out of the IDLE state (a maximum of
n
CLK IN cycles).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP2105 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:(666.40 k) |
| ADSP-2105 | 制造商:AD 制造商全稱:Analog Devices 功能描述:ADSP-2100 Family DSP Microcomputers |
| ADSP-2105BP-55 | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 13.824MHz 13.824MIPS 68-Pin PLCC 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ADSP-2105BP-55REEL | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| ADSP-2105BP-80 | 功能描述:IC DSP CONTROLLER 16BIT 68PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:ADSP-21xx 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
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